User's Manual

Eclipse2 Technical Manual V1.5 Page 11 of 16
Technical Description
The transceiver consists of three sub assemblies: Control Board, Interface board, and RF modules.
Control Board
The Control Board is a multi-layer, double side component mounted PCB assembly. The most
important parts of the base station, such as CPU, DSP and digital IF receiver, are embedded in this
master board, two 40-pin connectors on this board allows user inserting/removing it from the
interface (main) board.
The CPU (U1) is a single chip 32-bit RISC processor, it controls all the operating functions of the
base station. The support chips include a 16Mbyte Flash (U9) and 64Mbyte SDRAM (U7, U8). The
base station software and configuration databases are stored in the Flash memory. The system
serial bus and GPIO of the RISC processor are connected to the system interface board via two 40-
pin connectors.
The 10/100Mbps Ethernet Physical Layer single chip transceiver (U10) provides the interface
between RISC processor and the Ethernet. A serial ATA cable is used for connecting between the
Master board and System interface board.
The DSP (U2) is a 32-bit fixed-point digital signal processor, which provides the base band
processing including modulation, demodulation, RSSI/SINAD calculation, CTCSS encoding/decoding
and audio processing of the base station. The DSP software is modularized, the modulator,
demodulator, pre-emphasis, de-emphasis, filters and gain are individual modules, user can connect
or disconnect any module by the Service Kit software for different applications. The DSP also
controls the frequencies of the PLL chips within the RF modules. The digitized audio signal
interfaced to the CODEC of the system interface board is via the DSP serial port.
The digital IF receiver consists of an ADC (analogue to digital converter, U4) and a DDC (digital
down converter, U3). The pre-filtered analogue IF signal from the receiver module is fed to ADC,
converted to the digital IF and passed to the DDC via the parallel bus, the DDC mixes the incoming
digital IF with the internal Numerically Controlled Oscillator (NCO) frequency signal to produce the
0Hz IF, the DDC also provides decimating and further filtering for the IF signal. The output from
the DDC is in complex I/Q format, sent to the DSP for demodulating via the serial bus.
The clock of ADC, DDC and DSP is derived from the system interface board.
Interface (Main) board
The Interface (Main) board provides the interfaces among the Processor (main) board, RF modules
and external equipment. The function of the Interface board can be described as following sub
sections.
Audio signal processing
External audio signals from/to the base station are processed in this section.
The balanced audio input from RJ45 E/M Line connector or D25 system connector is passed, after
line matching transformer (T1) coupling, to a Trans-conductance amplifier (U11), the gain of the
amplifier is controlled by the RISC processor. The output of this amplification stage is then
amplitude limited, attenuated and filtered before send to the channel 1 of the CODEC (U12). The
CODEC encodes the analog audio to digital PCM signal send to the DSP via the serial bus.
The Microphone input from front panel RJ45 connector is amplified by op-amplifier (U16),
amplitude limited and attenuated then fed to the cannel 2 of the CODEC (U12). The CODEC
encodes the analog audio to digital PCM signal send to the DSP via the serial bus.
The AUX input signal from D25 system connector is DC coupled, filtered and amplitude limited by
the op-amplifier (U16), then fed into a 16-bit ADC (U17) to convert to the digital signal. The
digitized signal is send to the DSP via the serial bus. This AUX input is useful for low frequency