Service manual

RC2000 Service Manual Chapter 2 Theory of Operation 8
Research Concepts, Inc; 10679 Widmer; Lenexa, Kansas; USA 66215 WWW.RESEARCHCONCEPTS.COM
The 6264LP is an 8K x 8 low power static RAM (U5) with battery backup provided by circuitry on the digital
board. The static RAM uses 2 chip selects. CE2 is an active high chip select which is produced by U2. /CE1
is an active low chip select produced by U7. /CE1 insures that if a powerdown occurs during a write cycle the
contents of the static RAM will not be corrupted.
The MSM62X42BRS real time clock (RTC) (U6) integrated circuit (IC) maintains the system time and date.
The RTC includes a built-in crystal. The RTC has 2 chip selects. The /CS0 chip select is generated by the
address decode PLD. The CS1 chip select is tied to the micro-controller reset line (/RST). If the system
powers down during a write to the RTC the CS1 chip select prevents corrupt data from being written to the
RTC.
IC U7 is the Maxim MAX691 microprocessor supervisory circuit. This circuit provides a number of important
functions...
When the system is powered down this circuit provides battery power to the static RAM and the RTC.
On powerup, this IC holds the active low microprocessor reset line (/RST) low until the system power has
stabilized. The active high reset RST is used to initialize the 82C55. The /CE OUT output is used to control
one of the chip selects for the static RAM. This prevents corrupt data from being written to the RAM during
a powerdown. The /RST line performs a similar function with the RTC
The PFI input and the voltage divider formed by R5 and R6 is used to monitor the battery voltage. If the
battery voltage falls below 2.275 volts the /PFO output signals the micro-controller that the battery voltage is
low.
The 82C55 (U8) provides three 8 bit parallel I/O ports. Port A is configured for input, and ports B and C are
configured for output.
2.2.2 Keypad
The controller uses a 4 by 4 matrix keypad. The keyswitches are closed when the user depresses a key.
The micro-controller detects keystrokes by causing each row of the keypad to sequentially strobe low and
then monitoring the keypad column inputs. The keypad column inputs are pulled high with resistor network
RN4. The 74LS156 2 to 4 line decoder (U12) is used to strobe the keypad rows low. The decoder has open
collector outputs so that if two keys are depressed simultaneously there is no contention between decoder
outputs. When a key is depressed, that key's column input to the 82C55 will be low when the key's row is
strobed low by the decoder.
2.2.3 LCD Display
The LCD is connected to port 1 of the micro-controller. The LCD is used in 4-bit interface mode.
Potentiometer P1 adjusts the contrast of the LCD display.
2.2.4 Motor Control Circuitry
The azimuth and elevation axis motors are powered by a pair of MOSFET based H bridge control circuits.
The upper MOSFETs of each bridge are P channel type and the lower MOSFETs are N channel type. The
individual MOSFETs of the H bridges are controlled by a pair of state machines implemented via Intel
5C060 PLDs (U9 azimuth, U10 elevation). The state machine clocks are derived from the 3.33 MHz micro-
controller CLKOUT (clockout) output.
2.2.5 Description of the signals which control the state machine and which are generated by
the state machine