Service manual

RC2000 Service Manual Chapter 2 Theory of Operation 18
Research Concepts, Inc; 10679 Widmer; Lenexa, Kansas; USA 66215 WWW.RESEARCHCONCEPTS.COM
2.3.4 FET H-bridge
The DC drive signal is connected across the motor lines through the use of a solid-state switch
configuration known as an “H-bridge.” This name arises due to the switch elements being located on the
four vertical sections of an “H” and the motor located in the center section of the “H.”
Referring to the azimuth H-bridge portion of Figure 6, drive voltage is applied to the two output lines, AZ
Drive 1 and AZ Drive 2, of connector J2 buy turning on alternate pairs of FET devices. To apply forward
bias across the output lines, FETs Q2 and Q3 are biased on and FETs Q1 and Q4 are biased off. To
apply reverse bias, Q2 and Q3 are biased off while Q1 and Q4 are biased on. By allowing Q1 to remain
on, Q2 and Q3 to remain off, and rapidly switching Q4 off and on with a prescribed duty cycle, motor
speed can be controlled. By turning off Q1 and Q2, and turning on Q3 and Q4, a low resistance current
path is established between the two motor drive lines. This H-bridge mode acts as a dynamic motor
break. Metal oxide varistors across the two drive lines and in shunt from each of them to ground provide
a degree of protection from lighting strike induced voltage transients. A duplicate of the H-bridge,
consisting of Q5 - Q8, performs the switching functions for the elevation axis.
2.3.5 Biasing of the MOSFETs
The MOSFETs used for power switching on the drive board are of two types: P-channel and N-channel.
The P-channel devices, Q1, Q2 and Q5, Q6, make the connection between the positive supply and the
motor drive lines. N-channel devices, Q3, Q4 and Q7, Q8 are used for making connections between the
controllers power supply common node and the motor drive lines. Both the P-channel and N-channel
FET are turned on (biased to a low resistance condition) by application of the correct gate-to-source bias
voltage.
The bias circuitry for the P-channel FET, Q1, will be explained in detail. The other P-channel FETs, Q2,
Q5, and Q6, operate in a similar manner. In the off condition, a logic “0” is applied to the input of the
open-collector Darlington driver U2:C. The driver remains in the off condition, allowing the output (pin
14) to float to the drive supply input level. Since no current is flowing through the resistor pair R1 and
R2, the voltage presented to the FET gate is very nearly the same as the voltage on the source. This
gate-to-source voltage of near zero holds the FET in the “off” condition.
A logic “1” applied to the driver U2:C forces the driver output to the “on” condition with typical levels of
0.9 volts to 1.6 volts. This condition allows current to flow through resistor-pair R1-R2 with their junction
being held to 12 volts below the voltage on the FET source (typically 28 volts) by zener diode D1. This
voltage is presented to the FET gate which allows the FET to enter the “on” state.
The bias circuitry for the N-channel FET, Q3, will be explained in detail. The other N-channel FETs, Q4,
Q7, and Q8, operate in a similar manner. A logic “0” is applied to the input of the open-collector
Darlington driver U2:B. The driver remains in the off condition, allowing the output (pin 5) to float to the
12 volts prescribed by the network of R3 and zener diode D2. This voltage is presented to the gate of
Q3 through resistor R5 and forces the FET into the low resistance “on” state.
A logic “1” applied to the driver U2:B forces the driver output to the “on” condition with typical levels of
0.9 volts to 1.6 volts. This condition forces the junction of R3 and D2 to this level. This voltage is
presented to the FET gate which holds the FET in the “off” state.
The FET bias conditions and drive output polarity for various move commands may be found in the table
on the following page.