Datasheet
R01DS0041EJ0150 Rev.1.50 Page 219 of 221
Oct 18, 2013
RX210 Group REVISION HISTORY
REVISION HISTORY
RX210 Group Datasheet
Rev. Date
Description
Page Summary
0.50 Apr.15, 2011 — First edition, issued
0.90 Aug.10, 2011 1. Overview
4 Table 1.1 Outline of Specifications: Power supply voltage/ Operating frequency, changed
17, 21, 24,
26
Table 1.5 to Table 1.8 List of Pins and Pin Functions (Pin name: LVCMP2
CMPA2), changed
2. CPU
51 Table 2.14 Instructions that are Converted into Multiple Micro-Operations (multiplier: 32 × 32
64
bits), (memory source operand), added
4. I/O Registers
63 Table 5.1 List of I/O Registers (Address Order), SOSCWTCR, LOCOWTCR2, HOCOWTCR2,
added
114 to 116 Table 5.1 List of I/O Registers (Address Order): Interrupt source priority register, changed
5. Electrical Characteristics
85 to 137 Newly added
1.20 Nov 28, 2012 All Information on chip versions A, B, and C, corresponding descriptions and notes, added
48-pin products added, PLQP0080JA-A 14
14 mm, 0.65-mm pitch, package deleted
Features
1 Description changed
1. Overview
2 1.1 Outline of Specifications: Description, changed
2 to 5 Table 1.1 Outline of Specifications, changed
Note 1, added
6 Table 1.2 Comparison of Functions for Different Packages, changed
7 Table 1.3 List of Products, changed
8 to 10 Tables 1.4 to 1.7 List of Products, added
11 Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type: G item added
12 Figure 1.2 Block Diagram, changed
13 Table 1.8 Pin Functions: Power supply and On-chip emulator, changed
13 Table 1.8 Pin Functions: Multiplexed bus, added
18 Figure 1.4 Pin Assignments of the 100-Pin LQFP, changed
21 Figure 1.7 Pin Assignments of the 48-Pin LQFP, added
23 Table 1.9 List of Pins and Pin Functions (100-Pin TFLGA): Pin No. G4, changed
25 Table 1.10 List of Pins and Pin Functions (100-Pin LQFP): Pin No. 21, changed
28 Table 1.11 List of Pins and Pin Functions (80-Pin LQFP): Pin No. 19, changed
30 Table 1.12 List of Pins and Pin Functions (64-Pin LQFP): Pin No. 15, changed
3. Address Space
37 Figure 3.1 Memory Map in Each Operating Mode: Note 2, changed
4. I/O Registers
41 to 63 Table 4.1 List of I/O Registers (Address Order): Number of Access, changed
Voltage regulator control register, Timeout internal counter L, Timeout internal counter U, and PLL
power control register, added
63 Table 4.1 List of I/O Registers (Address Order): Notes 1 and 2, added
— Table 4.1 List of I/O Registers (Address Order): LOCO Wait Control Register 2 (LOCOWTCR2),
deleted
5. Electrical Characteristics
64 to 152 Description added
1.30 Jan 22, 2013 Features
1 On-chip flash memory for code, no wait states, On-chip SRAM, no wait states, Real-time clock,
Up to 15 communications channels, Up to 20 extended-function timers, changed
1.Overview
2 to 6 Table 1.1 Outline of Specifications, changed
7 Table 1.2 Comparison of Functions for Different Packages, changed
9 Table 1.4 List of Products Chip Version B: D Version (Ta = -40 to +85°C), changed
10 Table 1.5 List of Products Chip Version B: G Version (Ta = -40 to +105°C), changed
REVISION HISTORY