Datasheet

R01DS0041EJ0150 Rev.1.50 Page 192 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
Note: • These characteristics apply when noise is not superimposed on the power supply.
Note 1. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 2. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V
POR
, V
det0
,
V
det1,
and V
det2
for the POR/LVD.
Table 5.72 Power-on Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: VCC = AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V, T
a
= –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Voltage detection
level
Voltage detection circuit (LVD2)*
1
V
det2_0
4.00 4.15 4.30 V Figure 5.107
At falling edge
VCC
V
det2_1
3.85 4.00 4.15
V
det2_2
3.70 3.85 4.00
V
det2_3
3.55 3.70 3.85
V
det2_4
3.40 3.55 3.70
V
det2_5
3.25 3.40 3.55
V
det2_6
3.10 3.25 3.40
V
det2_7
2.95 3.10 3.25
V
det2_8
2.85 2.95 3.05
V
det2_9
2.70 2.80 2.90
V
det2_A
2.55 2.65 2.75
V
det2_B
2.40 2.50 2.60
V
det2_C
2.25 2.35 2.45
V
det2_D
2.10 2.20 2.30
V
det2_E
1.95 2.05 2.15
V
det2_F
1.80 1.90 2.00
V
CMPA2
1.18 1.33 1.48 EXVCCINP2 = 1
Internal reset time Power-on reset time t
POR
— 9 — ms Figure 5.104
Voltage monitoring 0 reset time t
LVD0
— 9 — Figure 5.105
Voltage monitoring 1 reset time t
LVD1
— 1.4 — Figure 5.106
Voltage monitoring 2 reset time t
LVD2
— 1.4 — Figure 5.107
Minimum VCC down time*
2
t
VOFF
200 — — µs Figure 5.103
Response delay time t
det
— — 200 µs Figure 5.104
LVD operation stabilization time (after LVD is enabled) Td
(E-A)
— — 15 µs Figure 5.106 and
Figure 5.107
Power-on reset enable time t
W(POR)
1 — — ms Figure 5.104
VCC = 0.9 V or
lower
Hysteresis width (LVD1 and LVD2) V
LVH
— 100 — mV When selection is
from among
VdetX_0 to 7.
— 50 — When selection is
from among
VdetX_8 to F.