Datasheet

R01DS0041EJ0150 Rev.1.50 Page 175 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
Note: • t
Pcyc
: PCLK cycle
Note 1. C
b
indicates the total capacity of the bus line.
Note 2. This applies when the SMR.CKS[1:0] bits = 00b and the SNFR.NFCS[2:0] bits = 010b while the SNFR.NFE bit = 1 and the digital
filter is enabled.
Table 5.60 Timing of On-Chip Peripheral Modules (6)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V, fPCLKB = up to 32 MHz,
T
a
= –40 to +105°C
When high-drive output is selected by the drive capacity register
Item Symbol Min.*
1
Max. Unit
Test
Conditions
Simple IIC
(Standard mode)
SDA input rise time t
Sr
— 1000 ns
Figure
5.98
SDA input fall time t
Sf
— 300 ns
SDA input spike pulse removal time t
SP
04 × t
pcyc
*
2
ns
Data input setup time t
SDAS
250 — ns
Data input hold time t
SDAH
0—ns
SCL, SDA capacitive load C
b
— 400 pF
Simple IIC
(Fast mode)
SCL, SDA input rise time t
Sr
20 + 0.1C
b
300 ns
Figure
5.98
SCL, SDA input fall time t
Sf
20 + 0.1C
b
300 ns
SCL, SDA input spike pulse removal time t
SP
04 × t
pcyc
*
2
ns
Data input setup time t
SDAS
100 — ns
Data input hold time t
SDAH
0—ns
SCL, SDA capacitive load C
b
— 400 pF