Datasheet

R01DS0041EJ0150 Rev.1.50 Page 174 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
Note: • t
IICcyc
: RIIC internal reference count clock (IICφ) cycle
Note 1. The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE
bits = 1.
Note 2. C
b
indicates the total capacity of the bus line.
Table 5.59 Timing of On-Chip Peripheral Modules (5)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V, fPCLKB = up to 32 MHz,
T
a
= –40 to +105°C
Item Symbol Min.*
1,
*
2
Max. Unit
Test
Conditions
RIIC
(Standard mode,
SMBus)
SCL input cycle time t
SCL
6 (12) × t
IICcyc
+ 1300 — ns Figure
5.98
SCL input high pulse width t
SCLH
3 (6) × t
IICcyc
+ 300 — ns
SCL input low pulse width t
SCLL
3 (6) × t
IICcyc
+ 300 — ns
SCL, SDA input rise time t
Sr
— 1000 ns
SCL, SDA input fall time t
Sf
— 300 ns
SCL, SDA input spike pulse removal time t
SP
01 (4) × t
IICcyc
ns
SDA input bus free time t
BUF
3 (6) × t
IICcyc
+ 300 — ns
Start condition input hold time t
STAH
t
IICcyc
+ 300 — ns
Restart condition input setup time t
STAS
1000 — ns
Stop condition input setup time t
STOS
1000 — ns
Data input setup time t
SDAS
t
IICcyc
+ 50 — ns
Data input hold time t
SDAH
0—ns
SCL, SDA capacitive load C
b
— 400 pF
RIIC
(Fast mode)
SCL input cycle time t
SCL
6 (12) × t
IICcyc
+ 600 — ns
Figure
5.98
SCL input high pulse width t
SCLH
3 (6) × t
IICcyc
+ 300 — ns
SCL input low pulse width t
SCLL
3 (6) × t
IICcyc
+ 300 — ns
SCL, SDA input rise time t
Sr
20 + 0.1C
b
300 ns
SCL, SDA input fall time t
Sf
20 + 0.1C
b
300 ns
SCL, SDA input spike pulse removal time t
SP
01 (4) × t
IICcyc
ns
SDA input bus free time t
BUF
3 (6) × t
IICcyc
+ 300 — ns
Start condition input hold time t
STAH
t
IICcyc
+ 300 — ns
Restart condition input setup time t
STAS
300 — ns
Stop condition input setup time t
STOS
300 — ns
Data input setup time t
SDAS
t
IICcyc
+ 50 — ns
Data input hold time t
SDAH
0—ns
SCL, SDA capacitive load C
b
— 400 pF