Datasheet

R01DS0041EJ0150 Rev.1.50 Page 173 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
Note 1. t
Pcyc
: PCLK cycle
Table 5.58 Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V, T
a
= –40 to +105°C
When high-drive output is selected by the drive capacity register
Item Symbol Min. Max. Unit*
1
Test Conditions
Simple
SPI
SCK clock cycle output (master) t
SPcyc
4 65536 t
Pcyc
C = 30 pF
Figure 5.91
SCK clock cycle input (slave) 6 65536
SCK input clock high pulse width t
SPCKWH
0.4 0.6 t
SPcyc
SCK input clock low pulse width t
SPCKWL
0.4 0.6 t
SPcyc
SCK output clock high pulse
width
2.7 V ≤ VCC ≤ 5.5 V t
SPCKWH
0.4 0.6 t
SPcyc
1.8 V ≤ VCC < 2.7 V 0.35 0.65
1.62 V ≤ VCC < 1.8 V 0.35 0.65
SCK output clock low pulse
width
2.7 V ≤ VCC ≤ 5.5 V t
SPCKWL
0.4 0.6 t
SPcyc
1.8 V ≤ VCC < 2.7 V 0.35 0.65
1.62 V ≤ VCC < 1.8 V 0.35 0.65
SCK clock rise/fall time t
SPCKr,
t
SPCKf
—20ns
Data input setup time
(Master)
2.7 V ≤ VCC ≤ 5.5 V t
SU
65 — ns C = 30 pF
Figure 5.92 to
Figure 5.97
1.8 V ≤ VCC < 2.7 V 75 —
1.62 V ≤ VCC < 1.8 V 80 —
Data input setup time (Slave) 40 —
Data input hold time t
H
40 — ns
SS input setup time t
LEAD
6—t
Pcyc
SS input hold time t
LAG
6—t
Pcyc
Data output delay time (Master) t
OD
—40ns
Data output delay time
(Slave)
2.7 V ≤ VCC ≤ 5.5 V — 65
1.8 V ≤ VCC < 2.7 V — 85
1.62 V ≤ VCC < 1.8 V — 95
Data output hold time t
OH
–10 — ns
Data rise/fall time t
Dr,
t
Df
—20ns
SS input rise/fall time t
SSLr,
t
SSLf
—20ns
Slave access time t
SA
—6t
Pcyc
C = 30 pF
Figure 5.96 and
Figure 5.97
Slave output release time t
REL
—6t
Pcyc