Datasheet

R01DS0041EJ0150 Rev.1.50 Page 171 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
Note 1. t
Pcyc
: PCLK cycle
[768 Kbytes/1 Mbyte of flash memory or 144/145 pins]
Item Symbol Min. Max. Unit*
1
Test Conditions
RSPI MOSI and MISO rise/
fall time
Output t
Dr,
t
Df
—20nsC = 30 pF
Figure 5.92 to
Figure 5.97
Input — 1 μs
SSL rise/fall time Output t
SSLr,
t
SSLf
—20ns
Input — 1 μs
Slave access time 2.7 V ≤ VCC ≤ 5.5 V t
SA
—6t
Pcyc
C = 30 pF
Figure 5.96 and
Figure 5.97
1.8 V ≤ VCC < 2.7 V — 7
1.62 V ≤ VCC < 1.8 V — 7
Slave output release time 2.7 V ≤ VCC ≤ 5.5 V t
REL
—5t
Pcyc
1.8 V ≤ VCC < 2.7 V — 6
1.62 V ≤ VCC < 1.8 V — 6
Table 5.57 Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V, T
a
= –40 to +105°C
When high-drive output is selected by the drive capacity register
Item Symbol Min. Max. Unit*
1
Test Conditions
RSPI RSPCK clock cycle Master t
SPcyc
24096t
Pcyc
C = 30pF
Figure 5.91
Slave 8 4096
RSPCK clock high
pulse width
Master 2.7 V ≤ VCC ≤ 5.5 V t
SPCKWH
(t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 3
—ns
1.8 V ≤ VCC < 2.7 V (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 3
—
1.62 V ≤ VCC < 1.8 V (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 10
—
Slave (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2
—
RSPCK clock low
pulse width
Master 2.7 V ≤ VCC ≤ 5.5 V t
SPCKWL
(t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 3
—ns
1.8 V ≤ VCC < 2.7 V (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 3
—
1.62 V ≤ VCC < 1.8 V (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 10
—
Slave (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2
—
RSPCK clock rise/fall
time
Output 2.7 V ≤ VCC ≤ 5.5 V t
SPCKr,
t
SPCKf
—10ns
1.8 V ≤ VCC < 2.7 V — 15
1.62 V ≤ VCC < 1.8 V — 20
Input — 1 μs