Datasheet

R01DS0041EJ0150 Rev.1.50 Page 170 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
[512 Kbytes or less of flash memory and 48 to 100 pins]
Table 5.56 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V, T
a
= –40 to +105°C
When high-drive output is selected by the drive capacity register
Item Symbol Min. Max. Unit*
1
Test Conditions
RSPI RSPCK clock cycle Master t
SPcyc
24096t
Pcyc
C = 30 pF
Figure 5.91
125 — ns
Slave 8 4096 t
Pcyc
RSPCK clock high
pulse width
Master 2.7 V ≤ VCC ≤ 5.5 V t
SPCKWH
(t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 3
—ns
1.8 V ≤ VCC < 2.7 V (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 3
—
1.62 V ≤ VCC < 1.8 V (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 10
—
Slave (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2
—
RSPCK clock low
pulse width
Master 2.7 V ≤ VCC ≤ 5.5 V t
SPCKWL
(t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 3
—ns
1.8 V ≤ VCC < 2.7 V (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 3
—
1.62 V ≤ VCC < 1.8 V (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2 – 10
—
Slave (t
SPcyc
– t
SPCKr
–
t
SPCKf
)/2
—
RSPCK clock rise/fall
time
Output 2.7 V ≤ VCC ≤ 5.5 V t
SPCKr,
t
SPCKf
—10ns
1.8 V ≤ VCC < 2.7 V — 15
1.62 V ≤ VCC < 1.8 V — 20
Input — 1 μs
Data input setup time Master 2.7 V ≤ VCC ≤ 5.5 V t
SU
50 — ns C = 30 pF
Figure 5.92 to
Figure 5.97
1.8 V ≤ VCC < 2.7 V 65 —
1.62 V ≤ VCC < 1.8 V 75 —
Slave 25 – t
Pcyc
—
Data input hold time Master t
H
t
Pcyc
—ns
Slave 20 + 2 × t
Pcyc
—
SSL setup time Master t
LEAD
18t
SPcyc
Slave 4 — t
Pcyc
SSL hold time Master t
LAG
18t
SPcyc
Slave 4 — t
Pcyc
Data output delay
time
Master 2.7 V ≤ VCC ≤ 5.5 V t
OD
—50ns
1.8 V ≤ VCC < 2.7 V — 55
1.62 V ≤ VCC < 1.8 V — 60
Slave 2.7 V ≤ VCC ≤ 5.5 V — 3 × t
Pcyc
+ 65
1.8 V ≤ VCC < 2.7 V — 3 × t
Pcyc
+ 85
1.62 V ≤ VCC < 1.8 V — 3 × t
Pcyc
+ 95
Data output hold time Master t
OH
0—ns
Slave 0 —
Successive
transmission delay
time
Master t
TD
t
SPcyc
+ 2 × t
Pcyc
8 × t
SPcyc
+ 2
× t
Pcyc
ns
Slave 4 × t
Pcyc
—