Datasheet

R01DS0041EJ0150 Rev.1.50 Page 169 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
5.3.6 Timing of On-Chip Peripheral Modules
Note 1. t
Pcyc
: PCLK cycle
Note 2. t
cac
: CAC count clock source cycle
Table 5.55 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V, T
a
= –40 to +105°C
When high-drive output is selected by the drive capacity register
Item Symbol Min. Max. Unit
Test
Conditions
I/O ports Input data pulse width t
PRW
1.5 — t
Pcyc
Figure 5.83
MTU/
TPU
Input capture input pulse width Single-edge setting t
TICW
1.5 — t
Pcyc
Figure 5.84
Both-edge setting 2.5 —
Timer clock pulse width Single-edge setting t
TCKWH,
t
TCKWL
1.5 — t
Pcyc
Figure 5.85
Both-edge setting 2.5 —
Phase counting
mode
2.5 —
POE POE# input pulse width t
POEW
1.5 — t
Pcyc
Figure 5.86
8-bit
timer
Timer clock pulse width Single-edge setting t
TMCWH,
t
TMCWL
1.5 — t
Pcyc
Figure 5.87
Both-edge setting 2.5 —
SCI Input clock cycle Asynchronous t
Scyc
4—t
Pcyc
Figure 5.88
Clock synchronous 6 —
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
—20ns
Input clock fall time t
SCKf
—20ns
Output clock cycle Asynchronous t
Scyc
16 — t
Pcyc
C = 30 pF
Figure 5.89
Clock synchronous 4 —
Output clock pulse width 2.7 V ≤ VCC ≤ 5.5 V t
SCKW
0.4 0.6 t
Scyc
1.8 V ≤ VCC < 2.7 V 0.35 0.65
1.62 V ≤ VCC < 1.8 V 0.35 0.65
Output clock rise time t
SCKr
—20ns
Output clock fall time t
SCKf
—20ns
Transmit data delay time
(master)
Clock synchronous t
TXD
—40ns
Transmit data delay time
(slave)
Clock
synchronous
2.7 V ≤ VCC ≤ 5.5 V — 65 ns
1.8 V ≤ VCC < 2.7 V — 85 ns
1.62 V ≤ VCC < 1.8 V — 95 ns
Receive data setup time
(master)
Clock
synchronous
2.7 V ≤ VCC ≤ 5.5 V t
RXS
65 — ns
1.8 V ≤ VCC < 2.7 V 75 — ns
1.62 V ≤ VCC < 1.8 V 80 — ns
Receive data setup time
(slave)
Clock synchronous 40 — ns
Receive data hold time Clock synchronous t
RXH
40 — ns
A/D
converter
Trigger input pulse width t
TRGW
1.5 — t
Pcyc
Figure 5.90
CAC CACREF input pulse width t
Pcyc
≤ t
cac
*
2
t
CACREF
4.5 t
cac
+ 3 t
Pcyc
—ns
t
Pcyc
> t
cac
*
2
5 t
cac
+ 6.5 t
Pcyc