Datasheet

R01DS0041EJ0150 Rev.1.50 Page 166 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
Table 5.52 Bus Timing (Multiplexed Bus) (1)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
fBCLK ≤ 25 MHz (BCLK pin output frequency ≤ 12.5 MHz), T
a
= –40 to +105°C, V
OH
= VCC × 0.5,
V
OL
= VCC × 0.5, I
OH
= –1.0 mA, I
OL
= 1.0 mA, C
L
= 30 pF
When normal output is selected by the drive capacity register
Item Symbol Min. Typ. Max. Unit
Address delay time t
AD
— 60 ns Figure 5.81 and
Figure 5.82
Byte control delay time t
BCD
—60ns
CS# delay time t
CSD
—60ns
RD# delay time t
RSD
—60ns
ALE delay time t
ALED
—60ns
Read data setup time t
RDS
40 — ns
Read data hold time t
RDH
0—ns
WR# delay time t
WRD
—60ns
Write data delay time t
WDD
—60ns
Write data hold time t
WDH
0—ns
WAIT# setup time t
WTS
40 — ns Figure 5.80
WAIT# hold time t
WTH
0—ns
Table 5.53 Bus Timing (Multiplexed Bus) (2)
Conditions: VCC = AVCC0 = 1.8 to 2.7 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
fBCLK ≤ 16 MHz (BCLK pin output frequency ≤ 8 MHz), T
a
= –40 to +105°C, V
OH
= VCC × 0.5,
V
OL
= VCC × 0.5, I
OH
= –1.0 mA, I
OL
= 1.0 mA, C
L
= 30 pF
When normal output is selected by the drive capacity register
Item Symbol Min. Typ. Max. Unit
Address delay time t
AD
— 90 ns Figure 5.81 and
Figure 5.82
Byte control delay time t
BCD
—90ns
CS# delay time t
CSD
—90ns
RD# delay time t
RSD
—90ns
ALE delay time t
ALED
—90ns
Read data setup time t
RDS
60 — ns
Read data hold time t
RDH
0—ns
WR# delay time t
WRD
—90ns
Write data delay time t
WDD
—90ns
Write data hold time t
WDH
0—ns
WAIT# setup time t
WTS
60 — ns Figure 5.80
WAIT# hold time t
WTH
0—ns