Datasheet

R01DS0041EJ0150 Rev.1.50 Page 149 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
Note 1. The time interval from the time P36 and P37 are configured for input and the main clock oscillator stopping bit
(MOSCCR.MOSTP) is set to 0 (operating) until the clock becomes available.
Table 5.44 Clock Timing
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V, T
a
= –40 to +105°C
Item Symbol Min. Typ. Max. Unit
Test
Conditions
EXTAL external clock input cycle time
t
EXcyc
50 — — ns Figure 5.60
EXTAL external clock input high pulse width
t
EXH
20 — — ns
EXTAL external clock input low pulse width
t
EXL
20 — — ns
EXTAL external clock rising time
t
EXr
—— 5ns
EXTAL external clock falling time
t
EXf
—— 5ns
EXTAL external clock input wait time*
1
t
EXWT
1——ms
Main clock oscillator oscillation frequency*
2
f
MAIN
1 — 20 MHz
Main clock oscillation stabilization time (crystal)*
2
t
MAINOSC
— 3 — ms Figure 5.61
Main clock oscillation stabilization time (ceramic resonator)*
2
t
MAINOSC
—50 µs
Main clock oscillation stabilization wait time (crystal)*
2
t
MAINOSCWT
—6—ms
Main clock oscillation stabilization wait time (ceramic resonator)*
2
t
MAINOSCWT
— 100 µs
LOCO clock cycle time
t
cyc
7.27 8 8.89 µs
LOCO clock oscillation frequency*
6
f
LOCO
112.5 125 137.5 kHz
LOCO clock oscillation stabilization wait time
t
LOCOWT
— — 20 µs Figure 5.62
HOCO clock oscillation frequency*
7
f
HOCO
31.680 32 32.320 MHz Ta = 0 to
50°C
36.495 36.864 37.233
39.600 40 40.400
49.500 50 50.500
31.520 32 32.480 Ta = -40 to
105°C
36.311 36.864 37.417
39.400 40 40.600
49.250 50 50.750
HOCO clock oscillation stabilization time 1
t
HOCO1
— — 300 µs Figure 5.63
HOCO clock oscillation stabilization time 2
t
HOCO2
— — 175 µs Figure 5.64
HOCO clock oscillation stabilization wait time
t
HOCOWT
— — 350 µs Figure 5.64
HOCO clock power supply stabilization time
t
HOCOP
— — 350 µs Figure 5.65
PLL input frequency
f
PLLIN
4 — 12.5 MHz
PLL circuit oscillation frequency
f
PLL
50 — 100 MHz
PLL clock oscillation stabilization time
PLL operation started
after main clock
oscillation has settled
t
PLL1
— — 500 µs Figure 5.66
PLL clock oscillation stabilization wait time
t
PLLWT1
1.5 — — ms
PLL clock oscillation stabilization time*
4
PLL operation started
before main clock
oscillation has settled
t
PLL2
—3.5*
3
— ms Figure 5.67
PLL clock oscillation stabilization wait
time*
4
t
PLLWT2
—7—ms
PLL clock power supply stabilization time (for chip version B only)
t
PLLPW
— — 30 µs Figure 5.68
Sub-clock oscillator oscillation frequency
f
SUB
— 32.768 — kHz
Sub-clock oscillation stabilization time*
5
t
SUBOSC
2 — — s Figure 5.69
Sub-clock oscillation stabilization wait time*
5
t
SUBOSCWT
4——s