User manual

 iSYSTEM, September 2014 13/23
9 Trace
The V850E2/Fx4 development system is based on a Renesas Fx4 Umbrella device that incorporates
an On-Chip Trace Unit, the OCT. The on-chip trace is based on messages and has limitations
compared to the in-circuit emulator where the complete CPU address, data and control bus is
available to the emulator in order to implement exact and advanced trace features.
9.1 On-Chip Trace Concept
For program trace, trace port sends a message only for every executed non-sequential instruction,
effectively on changes of a program flow. Each message contains the instruction type information and
a destination program counter. Based on this information, the debugger reconstructs complete
program flow by inserting sequential instructions between the recorded non-sequential instructions.
This can work as long as the debugger has a complete code image of the application (download file) in
order to know which sequential instructions are located between the non-sequential. For this reason, a
self-modifying code cannot be traced.
Transmitted OCT messages are appended with a time stamp information. That is a time of message,
not of execution. All sequential instructions being reconstructed by the debugger, relying on the code
image and inserted between the recorded addresses, do not contain exact time information. Any
interpolation with the recorded addresses containing valid time stamp would be misleading for the
user. Hence, all sequential instructions between the two non-sequential instructions, have the same
time stamp value.
Data trace can record all data access cycles issued by the CPU. However, no access to the CPU core
registers (R0-R31, FEPC, CTBP, etc) can be traced. Trace port bandwidth becomes quickly restrictive
with the data trace enabled since data trace usually generates 2 messages for a single traced data
access. When the number of trace messages exceeds the trace port bandwidth, an overflow message
is sent out in order to inform the user that messages were lost. From that point on until the next
synchronization message, there will be a gap in the trace display. It’s up to the user then to either limit
the traced data accesses, which yields less messages and thus no trace overflow, or to turn on the
non-real-time trace mode, which stalls the CPU in order for the trace port to transmit all messages in
the internal trace pipeline without loss. The non-real-time trace mode is turned on by checking the
Stall CPU to prevent overflows option in the Trigger/Qualifier configuration dialog.
9.2 On-Chip Trigger and Qualifier Configuration
The Qualifier pane defines which CPU cycles are recorded by the trace. Complete program flow can
be either recorded or not. Additionally, program flow recording can be limited to a specific part of an
application code. Use Trace ON and Trace OFF option to do that. Record CMOV and Record OTM
control the recording of Conditional Move instructions and Ownership Trace Messages.
Data accesses can be all recorded but this can easily lead to trace overflows. As an alternative, 4 data
qualifier address ranges can be defined for the data accesses. See the next picture for an example.