_ V9.12. 184 Technical Notes Renesas V850E2/Fx4 Family In-Circuit Emulation This document is intended to be used together with the CPU reference manual provided by the silicon vendor. This document assumes knowledge of the CPU functionality and the terminology and concepts defined and explained in the CPU reference manual. Basic knowledge of winIDEA is also necessary. This document deals with specifics and advanced details and it is not meant as a basic or introductory text.
1 Introduction The Renesas V850E2/Fx4 ActiveGT POD is built from the iC3000/ActiveGT platform from iSYSTEM and a special V850E2/Fx4 emulation POD produced by Renesas. The two parts are connected with a wide flex cable that carries JTAG debug and Nexus trace signals. Debug Features Execution breakpoints Access breakpoints Real-time memory access Trace Profiler Execution Coverage Flash Security and Mask Options programming 1.
2 Emulation Options 2.1 Hardware Options In-Circuit Emulator Options dialog, Hardware page There are no user settable options here. The Emulation memory is actually a flash memory inside the Fx4 Umbrella device on the Renesas POD. There is also no need for the Shadow Memory as the Real-Time access is supported by the debug interface by default. 2.2 CPU Configuration Select the emulated CPU family, the POD and the target device being emulated. CPU Setup Opens the CPU Setup dialog.
In-Circuit Emulator Options dialog, Vcc/Clock Setup page No option here, as well. The POD power is provided so that the emulator can be used standalone, that is, without being connected to a target board. As soon as the target is connected, the target power has to be applied. Note the correct sequencing of the emulator and target power. There is no programmable clock control available from winIDEA. Check the Renesas V850E2/Fx4 User Manual to familiarize yourself with the microcontroller clock controller.
2.5 JTAG Scan Speed JTAG Scan Speed definition Scan speed JTAG Scan Speed is automatically set to the Free mode. The free running JTAG clock is required by the V850E2 debug interface.
3 CPU Setup 3.1 CPU Options The CPU Setup, Options page provides some emulation settings, common to most CPU families and all emulation modes. Settings that are not valid for currently selected CPU or emulation mode are disabled. If none of these settings is valid, this page is not shown. CPU Setup, Options page Stop CPU Activities When Stopped When this option is checked, most of the peripheral functions are stopped when the application is stopped.
3.2 Debugging Options This pane exposes two options related to a memory access. Displayed below are default settings. If the settings are reversed, it allows a post-mortem examination of the internal RAM that would otherwise be cleared by the debugger initialization. Ignore access errors Any access to an undefined address space or non-initialized internal RAM returns an error status. This is displayed with question marks ‘?’ all over the memory window when such address base is given.
3.3 Reset Options Latch target RESET When the option is checked, the debugger latches active target reset until it gets processed. This yields a delay between the target reset and restart of the application from reset. If this delay is not acceptable for a specific application, the option should be unchecked. An example is an application where the CPU is periodically set into a power save mode and then waken up e.g. every 6ms by an external reset circuit.
The trace clock frequency can be checked in the Plugins/Measurement window. The Trace Clock is measured on the Renesas POD trace connector, while the CPU Clock is calculated from the Nexus clock divider setting above. If the trace clock exceeds the hardware limits, then the trace window will contain errors or be blank even in Record everything mode. The displayed frequencies are shown for informational purposes only.
4 Flash Mask Options and Security Flags The dialog under the Hardware/Tools/FLASH menu provide access to the V850E2/Fx4 Flash Mask option bits. Certain options need the CPU to go over reset to take effect. Please refer to the Fx4 User Manual. Note: Programming of the Security Flags has been disabled to prevent locking the in-circuit emulation device. The flags are intended for end product protection, and are available for iC5000 and iC3000/iCard environments.
5 Memory Access V850E2 debug interface features a real-time memory access, that does not require user program to be stopped and allows reading the memory while the application is running. Note that large amounts of memory read affect the application performance. 6 Hardware Breakpoints Access breakpoints are configured by opening the Debug/Hardware Breakpoints dialog. Two breakpoints are provided. Note that they are shared with the execution breakpoints from the Debug/Breakpoints dialog.
7 OSEK Debug Support Enable OSEK support by selecting ‘ORTI (AUTOSAR,OSEK,CMX)’ selection in the ‘Debug/Operating System’ dialog and then press the ‘Setup’ button. Specify the path to the OSEK ORTI file, where the necessary debug information is kept. 8 Getting Started 1) 2) 3) 4) 5) Connect the system. Power up the emulator and then power up the target. Execute debug reset. The CPU should stop on reset location 0x0.
9 Trace The V850E2/Fx4 development system is based on a Renesas Fx4 Umbrella device that incorporates an On-Chip Trace Unit, the OCT. The on-chip trace is based on messages and has limitations compared to the in-circuit emulator where the complete CPU address, data and control bus is available to the emulator in order to implement exact and advanced trace features. 9.
Trace Qualifier The Watchpoint Trace width and Data Message Type are shown in their default, recommended settings. Other settings are available to aid solving any more demanding issues.
9.3 Trace Examples Analyzer window is opened from the View menu. Before using trace for the first time please refer to winIDEA Contents Help, Analyzer Window section (or alternatively to the standalone Analyzer.pdf document). A screenshot of the Trigger dialog shows that any trigger item can also function as a qualifier, as a Trace On or Off switch, or as an input to the Trigger Sequence Engine coupled with an event counter.
Before the program is set to run or while it is running already, activate the trace recording by the ‘Trace begin’ tool bar or the CTRL+B shortcut key. The trace stops recording when the program execution is stopped. After the trace stops recording, the collected information is analyzed and displayed. Select a start ‘Immediately’ or ‘On Trigger’ when the trace should record only until the trace buffer gets full.
Example 2 Trigger Settings Now activate the trace and run the program. When the trigger event occurs, the trace will stop recording and display the recorded program. Let’s take a look at the trace record as there are some differences in the display comparing to the standard in-circuit emulator trace, where the program flow is obtained by recording activities directly on the CPU bus.
Example 2 Trace Result When the trigger occurs, trace port outputs a special trigger message called Watchpoint, frame 0 above. This is detected by the external trace hardware and recorded as a trigger event. Recorded trigger message is depicted with a red frame in the trace window. In this example, we can see that actual Type_Simple() function started 3 frames after the Watchpoint message.
Example 3: The trace will start recording (instructions and data accesses) after the function Type_Simple() is executed for the fifth time. Let‘s configure a new trigger called e.g. ‘Trigger 1’. Reuse the settings from the previous example. All remains the same except that Execution Watchpoint 1 is now configured for the sequencer respectively SW4 state of the sequencer instead for the trigger. The user can configure a sequence of up to 4 states (SW1-SW4) in the ‘Sequencer’ field.
Example 3 Qualifier Settings Start the trace and run the application from reset on. After Type_Simple() is executed five times, the trace will trigger and normally display the program around the trigger message. Let’s analyze the trace record. It’s possible that the trace record will contain the overflow messages. That happens due to the enabled data trace. Occurrence of overflows depends on the code, which can generate an arbitrary number of data accesses.
Example 3 Trace Result The first one is to use the non-real-time trace mode, which stalls the CPU until the FIFO buffer becomes ready for new messages and then resumes the execution. This trace mode is turned on by checking the ‘Stall CPU to avoid overflows’ option in the Trigger pane. Since this is a severe intrusion in the real-time program execution it is not a recommended solution unless the user is fully aware of the consequences.
Example 4: Configure trace to record only data accesses to the 32-bit global variable named iCounter. Following picture shows the necessary settings. Example 4 Qualifier Settings This setting yields a trace recording without overflow errors. See the next screenshot.
Example 4 Trace Result 10 Coverage Refer to winIDEA Contents Help, Coverage Concepts section for Coverage theory and background. Refer to winIDEA Contents Help, Analyzer Window section (or alternatively to the standalone Analyzer.pdf document) for information on Coverage user interface and use. 11 Profiler Refer to winIDEA Contents Help, Profiler Concepts section for Profiler theory and background. Refer to winIDEA Contents Help, Analyzer Window section (or alternatively to the standalone Analyzer.
