Datasheet

CHAPTER 5 CLOCK GENERATORS
User’s Manual U18172EJ3V0UD
89
Figure 5-14. Status Transition of Low-Speed Internal Oscillator
LSRSTOP = 0
Cannot be stopped
Can be stopped
Clock source of
WDT is selected
by software
Note
Clock source of
WDT is fixed to f
RL
LSRSTOP = 1
V
DD > 2.1 V ±0.1 V
Reset signal
Power
application
Reset by
power-on clear
Low-speed internal
oscillator can be stopped
Low-speed internal
oscillator cannot be stopped
Low-speed internal
oscillator stops
Select by option byte
if low-speed internal oscillator
can be stopped or not
Note The clock source of the watchdog timer (WDT) is selected from fX or fRL, or it may be stopped. For details,
refer to CHAPTER 8 WATCHDOG TIMER.