Datasheet
CHAPTER 5 CLOCK GENERATORS
User’s Manual U18172EJ3V0UD
77
The fastest instruction of the 78K0S/KU1+ is executed in two CPU clocks. Therefore, the relationship between the
CPU clock (f
CPU) and the minimum instruction execution time is as shown in Table 5-2.
Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time
Minimum Instruction Execution Time: 2/fCPU CPU Clock (fCPU)
Note 1
High-speed internal oscillation clock
(at 8.0 MHz (TYP.))
Crystal/ceramic oscillation clock
Note 2
or external clock input (at 10.0 MHz)
fX 0.25
μ
s 0.2
μ
s
fX/2 0.5
μ
s 0.4
μ
s
fX/2
2
1.0
μ
s 0.8
μ
s
fX/2
3
2.0
μ
s 1.6
μ
s
fX/2
4
4.0
μ
s 3.2
μ
s
Notes 1. The CPU clock (high-speed internal oscillation clock, crystal/ceramic oscillation clock
Note 2
, or external
clock input) is selected by the option byte.
2.
μ
PD78F920x only
(2) Low-speed internal oscillation mode register (LSRCM)
This register is used to select the operation mode of the low-speed internal oscillator (240 kHz (TYP.)).
This register is valid when it is specified by the option byte that the low-speed internal oscillator can be stopped
by software. If it is specified by the option byte that the low-speed internal oscillator cannot be stopped by
software, setting of this register is invalid, and the low-speed internal oscillator continues oscillating. In addition,
the source clock of WDT is fixed to the low-speed internal oscillator. For details, refer to CHAPTER 8
WATCHDOG TIMER.
LSRCM can be set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LSRCM to 00H.
Figure 5-4. Format of Low-Speed internal oscillation Mode Register (LSRCM)
Address: FF58H, After reset: 00H, R/W
Symbol 7 6 5 4 3 2 1 <0>
LSRCM 0 0 0 0 0 0 0 LSRSTOP
LSRSTOP
Oscillation/stop of low-speed internal oscillator
0
Low-speed internal oscillates
1
Low-speed internal oscillator stops
<R>