Datasheet

CHAPTER 5 CLOCK GENERATORS
User’s Manual U18172EJ3V0UD
75
Figure 5-1. Block Diagram of Clock Generators (2/2)
(2)
μ PD78F950x
EXCLK/P23
f
X
f X
2
PCC1
Selector
CPU clock
(f
CPU )
Internal bus
Internal bus
Preprocessor clock
control register (PPCC)
Processor clock
control register (PCC)
STOP
PPCC1 PPCC0
f XP
2
2
f XP
f X
2
2
f RL
LSRSTOP
CPU
Selector
Prescaler
Clock to peripheral
hardware (f
XP )
8-bit timer H1,
watchdog timer
Option byte
1: Cannot be stopped.
0: Can be stopped.
Low-speed internal oscillation
mode register (LSRCM)
Low-speed
internal
oscillator
Prescaler
System clock
oscillator
Note
External clock
input
High-speed
internal
oscillation
Watchdog timer
Note Select the high-speed internal oscillator or external clock input circuit as the system clock source by using
the option byte.
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