Datasheet
APPENDIX D LIST OF CAUTIONS
User’s Manual U18172EJ3V0UD
328
(7/15)
Chapter
Classification
Function Details of
Function
Cautions Page
Chapter 7
Soft
8-bit timer
H1
PWM output Make sure that the CMP11 register setting value (M) and CMP01 register setting
value (N) are within the following range.
00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH
p. 141
Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values. p. 149
After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated. However, at the first write, if “1” and “x” are set for WDCS4
and WDCS3 respectively and the watchdog timer is stopped, then the internal
reset signal does not occur even if the following are executed.
• Second write to WDTM
• 1-bit memory manipulation instruction to WDTE
• Writing of a value other than “ACH” to WDTE
p. 150
WDTM cannot be set by a 1-bit memory manipulation instruction. p. 150
WDTM:
Watchdog timer
mode register
When using the flash memory programming by self programming, set the overflow
time for the watchdog timer so that enough overflow time is secured (Example 1-
byte writing: 200
μ
s MIN., 1-block deletion: 10 ms MIN.).
p. 150
If a value other than ACH is written to WDTE, an internal reset signal is
generated.
p. 150
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
p. 150
Soft
WDTE:
Watchdog timer
enable register
The value read from WDTE is 9AH (this differs from the written value (ACH)). p. 150
When “low-
speed internal
oscillator cannot
be stopped” is
selected by
option byte
In this mode, operation of the watchdog timer cannot be stopped even during
STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the low-
speed internal oscillation clock can be selected as the count source, so clear the
watchdog timer using the interrupt request of TMH1 before the watchdog timer
overflows after STOP instruction execution. If this processing is not performed,
an internal reset signal is generated when the watchdog timer overflows after
STOP instruction execution.
p. 151
Chapter 8
Hard
Watchdog
timer
When “low-
speed internal
oscillator can be
stopped by
software” is
selected by
option byte
In this mode, watchdog timer operation is stopped during HALT/STOP instruction
execution. After HALT/STOP mode is released, counting is started again using
the operation clock of the watchdog timer set before HALT/STOP instruction
execution by WDTM. At this time, the counter is not cleared to 0 but holds its
value.
p. 153
Soft
Sampling time
and A/D
conversion time
The above sampling time and conversion time do not include the clock frequency
error. Select the sampling time and conversion time such that Notes 2 and 3
above are satisfied, while taking the clock frequency error into consideration (an
error margin maximum of ±5% when using the high-speed internal oscillator).
p. 158
In
μ
PD78F920x, VSS functions alternately as the ground potential of the A/D
converter. Be sure to connect V
SS to a stabilized GND (= 0 V).
p. 159
Hard
Block Diagram
In
μ
PD78F920x, VDD functions alternately as the A/D converter reference voltage
input. When using the A/D converter, stabilize V
DD at the supply voltage used
(2.7 to 5.5 V).
p. 159
Chapter 9
Soft
A/D
converter
(
μ
PD78F9
20x only)
ADM: A/D
converter mode
register
The above sampling time and conversion time do not include the clock frequency
error. Select the sampling time and conversion time such that Notes 3 and 4
above are satisfied, while taking the clock frequency error into consideration (an
error margin maximum of ±5% when using the high-speed internal oscillator).
p. 163