Datasheet

APPENDIX D LIST OF CAUTIONS
User’s Manual U18172EJ3V0UD
325
(4/15)
Chapter
Classification
Function Details of
Function
Cautions Page
Even if the OVF00 flag is cleared before the next count clock is counted (before
TM00 becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag
is re-set newly and clear is disabled.
pp. 96,
126
Chapter 6
Soft
16-bit
timer/
event
counters
00
(
μ PD78F
920x
only)
TMC00: 16-bit
timer mode
control register
00
The capture operation is performed at the fall of the count clock. An interrupt
request input (INTTM0n0), however, occurs at the rise of the next count clock.
pp. 96,
127
The timer operation must be stopped before setting CRC00. pp. 97,
125
When the clear & start mode entered on a match between TM00 and CR000 is
selected by 16-bit timer mode control register 00 (TMC00), CR000 should not be
specified as a capture register.
pp. 97,
124
Hard
CRC00:
Capture/
compare control
register 00
To ensure the reliability of the capture operation, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode
register 00 (PRM00) (refer to Figure 6-18).
pp. 97,
127
Timer operation must be stopped before setting other than OSPT00. pp. 98,
125
If LVS00 and LVR00 are read, 0 is read. pp. 98,
125
OSPT00 is automatically cleared after data is set, so 0 is read. pp. 98,
125
Soft
Do not set OSPT00 to 1 other than in one-shot pulse output mode. pp. 98,
125
Hard
A write interval of two cycles or more of the count clock selected by prescaler
mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively.
pp. 98,
125
Soft
TOC00: 16-bit
timer output
control register
00
When the TOE00 is 0, set the TOE00, LVS00, and LVR00 at the same time with
the 8-bit memory manipulation instruction. When the TOE00 is 1, the LVS00 and
LVR00 can be set with the 1-bit memory manipulation instruction.
p. 99
Always set data to PRM00 after stopping the timer operation. pp. 99,
125
Soft
If the valid edge of the TI000 pin is to be set as the count clock, do not set the
clear/start mode and the capture trigger at the valid edge of the TI000 pin.
pp. 99,
127
Hard
PRM00:
Prescaler mode
register 00
In the following cases, note with caution that the valid edge of the TI0n0 pin is
detected.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the
operation of the 16-bit timer counter 00 (TM00) is enabled
→If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00
operation is enabled.
<2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00
operation is then enabled after a low level is input to the TI0n0 pin
→If the falling edge or both rising and falling edges are specified as the valid
edge of the TI0n0 pin, a falling edge is detected immediately after the TM00
operation is enabled.
<3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00
operation is then enabled after a high level is input to the TI0n0 pin
→If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00
operation is enabled.
pp. 100,
129