Datasheet

CHAPTER 3 CPU ARCHITECTURE
User’s Manual U18172EJ3V0UD
30
Figure 3-2. Memory Map ( μ PD78F9201, 78F9501)
Special function registers
(SFR)
256 × 8 bits
Internal high-speed RAM
128 × 8 bits
Flash memory
2,048 × 8 bits
Program memory
space
Data memory
space
Use prohibited
FFFFH
FF00H
FEFFH
FE80H
FE7FH
0800H
07FFH
0000H
Program area
Option byte area
Program area
CALLT table area
Vector table area
07FFH
0040H
003FH
0014H
0013H
0000H
Protect byte area
0082H
0081H
0080H
007FH
Remark The option byte and protect byte are 1 byte each.
<R>