Datasheet

CHAPTER 18 INSTRUCTION SET OVERVIEW
User’s Manual U18172EJ3V0UD
289
Flag Mnemonic Operand Bytes Clocks Operation
Z AC CY
A, #byte 2 4 A − byte
× × ×
saddr, #byte 3 6 (saddr) − byte
× × ×
A, r 2 4 A − r
× × ×
A, saddr 2 4 A − (saddr)
× × ×
A, !addr16 3 8 A − (addr16)
× × ×
A, [HL] 1 6 A − (HL)
× × ×
CMP
A, [HL + byte] 2 6 A − (HL + byte)
× × ×
ADDW AX, #word 3 6 AX, CY ← AX + word
× × ×
SUBW AX, #word 3 6 AX, CY ← AX − word
× × ×
CMPW AX, #word 3 6 AX − word
× × ×
r 2 4 r ← r + 1
× ×
INC
saddr 2 4 (saddr) ← (saddr) + 1
× ×
r 2 4 r ← r − 1
× ×
DEC
saddr 2 4 (saddr) ← (saddr) − 1
× ×
INCW rp 1 4 rp ← rp + 1
DECW rp 1 4 rp ← rp − 1
ROR A, 1 1 2 (CY, A7 ← A0, Am−1 ← Am) × 1
×
ROL A, 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1
×
RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am−1 ← Am) × 1
×
ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1
×
saddr.bit 3 6 (saddr.bit) ← 1
sfr.bit 3 6 sfr.bit ← 1
A.bit 2 4 A.bit ← 1
PSW.bit 3 6 PSW.bit ← 1
× × ×
SET1
[HL].bit 2 10 (HL).bit ← 1
saddr.bit 3 6 (saddr.bit) ← 0
sfr.bit 3 6 sfr.bit ← 0
A.bit 2 4 A.bit ← 0
PSW.bit 3 6 PSW.bit ← 0
× × ×
CLR1
[HL].bit 2 10 (HL).bit ← 0
SET1 CY 1 2 CY ← 1 1
CLR1 CY 1 2 CY ← 0 0
NOT1 CY 1 2 CY ← CY
×
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).