Datasheet

CHAPTER 18 INSTRUCTION SET OVERVIEW
User’s Manual U18172EJ3V0UD
288
Flag Mnemonic Operand Bytes Clocks Operation
Z AC CY
A, #byte 2 4 A, CY ← A − byte − CY
× × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) − byte − CY
× × ×
A, r 2 4 A, CY ← A − r − CY
× × ×
A, saddr 2 4 A, CY ← A − (saddr) − CY
× × ×
A, !addr16 3 8 A, CY ← A − (addr16) − CY
× × ×
A, [HL] 1 6 A, CY ← A − (HL) − CY
× × ×
SUBC
A, [HL + byte] 2 6 A, CY ← A − (HL + byte) − CY
× × ×
A, #byte 2 4 A ← A ∧ byte
×
saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte
×
A, r 2 4 A ← A ∧ r
×
A, saddr 2 4 A ← A ∧ (saddr)
×
A, !addr16 3 8 A ← A ∧ (addr16)
×
A, [HL] 1 6 A ← A ∧ (HL)
×
AND
A, [HL + byte] 2 6 A ← A ∧ (HL + byte)
×
A, #byte 2 4 A ← A ∨ byte
×
saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte
×
A, r 2 4 A ← A ∨ r
×
A, saddr 2 4 A ← A ∨ (saddr)
×
A, !addr16 3 8 A ← A ∨ (addr16)
×
A, [HL] 1 6 A ← A ∨ (HL)
×
OR
A, [HL + byte] 2 6 A ← A ∨ (HL + byte)
×
A, #byte 2 4 A ← A ∨ byte
×
saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte
×
A, r 2 4 A ← A ∨ r
×
A, saddr 2 4 A ← A ∨ (saddr)
×
A, !addr16 3 8 A ← A ∨ (addr16)
×
A, [HL] 1 6 A ← A ∨ (HL)
×
XOR
A, [HL + byte] 2 6 A ← A ∨ (HL + byte)
×
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).