Datasheet

CHAPTER 18 INSTRUCTION SET OVERVIEW
User’s Manual U18172EJ3V0UD
287
Flag Mnemonic Operand Bytes Clocks Operation
Z AC CY
rp, #word 3 6 rp ← word
AX, saddrp 2 6 AX ← (saddrp)
saddrp, AX 2 8 (saddrp) ← AX
AX, rp
Note
1 4 AX ← rp
MOVW
rp, AX
Note
1 4 rp ← AX
XCHW AX, rp
Note
1 8 AX ↔ rp
A, #byte 2 4 A, CY ← A + byte
× × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte
× × ×
A, r 2 4 A, CY ← A + r
× × ×
A, saddr 2 4 A, CY ← A + (saddr)
× × ×
A, !addr16 3 8 A, CY ← A + (addr16)
× × ×
A, [HL] 1 6 A, CY ← A + (HL)
× × ×
ADD
A, [HL + byte] 2 6 A, CY ← A + (HL + byte)
× × ×
A, #byte 2 4 A, CY ← A + byte + CY
× × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY
× × ×
A, r 2 4 A, CY ← A + r + CY
× × ×
A, saddr 2 4 A, CY ← A + (saddr) + CY
× × ×
A, !addr16 3 8 A, CY ← A + (addr16) + CY
× × ×
A, [HL] 1 6 A, CY ← A + (HL) + CY
× × ×
ADDC
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY
× × ×
A, #byte 2 4 A, CY ← A − byte
× × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) − byte
× × ×
A, r 2 4 A, CY ← A − r
× × ×
A, saddr 2 4 A, CY ← A − (saddr)
× × ×
A, !addr16 3 8 A, CY ← A − (addr16)
× × ×
A, [HL] 1 6 A, CY ← A − (HL)
× × ×
SUB
A, [HL + byte] 2 6 A, CY ← A − (HL + byte)
× × ×
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (f
CPU) selected by the processor clock control register
(PCC).