Datasheet

CHAPTER 16 FLASH MEMORY
User’s Manual U18172EJ3V0UD
266
(2) Write to internal verify
<1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4)
<2> Specification of source data for write
<3> Execution of byte write → Error check (<1> to <10> in 16.8.8)
<4> <3> is repeated until all data are written.
<5> Execution of internal verify → Error check (<1> to <11> in 16.8.9)
<6> Mode is shifted from self programming mode to normal mode (<1> to <6> in 16.8.5)
Figure 16-26. Example of Operation When Command Execution Time Should Be Minimized
(from Write to Internal Verify)
<6> Shift to normal mode
Abnormal
<1> Shift to self programming
mode
Write to internal verify
<3> Execute byte write command
<5> Execute internal verify command
<3> Check execution result
(VCERR and WEPRERR flags)
<5> Check execution result
(VCERR and WEPRERR flags)
Normal termination
Normal
Abnormal
Normal
Figure 16- 22
<1> to <10>
Figure 16-
23
<1> to <11>
Figure 16-19
<1> to <6>
<2> Set source data for write
<4> All data written?
Yes
No
Figure 16-18
<1> to <7>
Abnormal termination
Note
Note Perform processing to shift to normal mode in order to return to normal processing.
Remark <1> to <6> in Figure 16-26 correspond to <1> to <6> in 16.8.10 (2) above.