Datasheet

CHAPTER 14 LOW-VOLTAGE DETECTOR
User’s Manual U18172EJ3V0UD
210
(2) Low-voltage detection level select register (LVIS)
This register selects the low-voltage detection level.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H
Note
.
Figure 14-3. Format of Low-Voltage Detection Level Select Register (LVIS)
Address: FF51H, After reset: 00H
Note
R/W
Symbol 7 6 5 4 3 2 1 0
LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVIS0
LVIS3 LVIS2 LVIS1 LVIS0 Detection level
0 0 0 0 VLVI0 (4.3 V ±0.2 V)
0 0 0 1 VLVI1 (4.1 V ±0.2 V)
0 0 1 0 VLVI2 (3.9 V ±0.2 V)
0 0 1 1 VLVI3 (3.7 V ±0.2 V)
0 1 0 0 VLVI4 (3.5 V ±0.2 V)
0 1 0 1 VLVI5 (3.3 V ±0.15 V)
0 1 1 0 VLVI6 (3.1 V ±0.15 V)
0 1 1 1 VLVI7 (2.85 V ±0.15 V)
1 0 0 0 VLVI8 (2.6 V ±0.1 V)
1 0 0 1 VLVI9 (2.35 V ±0.1 V)
Other than above Setting prohibited
Note For a reset by LVI, the value of LVIS is not initialized.
Cautions 1. Bits 4 to 7 must be set to 0.
2. If a value other than the above is written during LVI operation, the value becomes
undefined at the very moment it is written, and thus be sure to stop LVI (bit
7(LVION) = 0 on the LVIM register) before writing.