Datasheet

CHAPTER 12 RESET FUNCTION
User’s Manual U18172EJ3V0UD
200
Figure 12-4. Reset Timing by RESET Input in STOP Mode
<1> With high-speed internal oscillation clock or external clock input
Hi-Z
RESET
Port pin
Delay
Normal
operation
in progress
CPU clock
Reset period
(oscillation stops)
Normal operation (reset processing, CPU clock)
Internal reset signal
High-speed internal oscillation clock or
external clock input
Delay
Operation stops because option
byte is referenced
Note
.
Stop status
(oscillation stops)
STOP instruction is executed.
100 ns (TYP.)
100 ns (TYP.)
Note The operation stop time is 277
μ s (MIN.), 544 μ s (TYP.), and 1.075 ms (MAX.).
<2> With crystal/ceramic oscillation clock (
μ PD78F920x only)
Hi-Z
RESET
Port pin
Delay
Normal
operation
in progress
CPU clock
Normal operation
(reset processing, CPU clock)
Internal reset signal
Crystal/ceramic
oscillation clock
Delay
Operation stops because option
byte is referenced
Note
.
Reset period
(oscillation stops)
Stop status
(oscillation stops)
STOP instruction is executed.
Oscillation stabilization
time (2
10
/fX to 2
17
/fX)
100 ns (TYP.) 100 ns (TYP.)
Note The operation stop time is 276 μ s (MIN.), 544 μ s (TYP.), and 1.074 ms (MAX.).
Remarks 1. For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 13
POWER-ON-CLEAR CIRCUIT and CHAPTER 14 LOW-VOLTAGE DETECTOR.
2. f
X: System clock oscillation frequency
<R>