Datasheet

CHAPTER 12 RESET FUNCTION
User’s Manual U18172EJ3V0UD
199
Figure 12-3. Timing of Reset by Overflow of Watchdog Timer
<1> With high-speed internal oscillation clock or external clock input
Hi-Z
Port pin
Normal operation
in progress
CPU clock
Reset period
(oscillation stops)
Normal operation (reset processing, CPU clock)
Internal reset signal
High-speed internal oscillation clock or
external clock input
Operation stops because option
byte is referenced
Note
.
Watchdog overflow
Note The operation stop time is 277 μ s (MIN.), 544 μ s (TYP.), and 1.075 ms (MAX.).
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
<2> With crystal/ceramic oscillation clock (
μ PD78F920x only)
Hi-Z
Port pin
Normal operation
in progress
Reset period
(oscillation stops)
Oscillation stabilization
time (2
10
/f X to 2
17
/f X )
Normal operation
(reset processing, CPU clock)
Internal reset signal
Crystal/ceramic
oscillation clock
Operation stops because option
byte is referenced
Note
.
CPU clock
Watchdog overflow
Note The operation stop time is 276
μ s (MIN.), 544 μ s (TYP.), and 1.074 ms (MAX.).
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remark f
X: System clock oscillation frequency
<R>