Datasheet

CHAPTER 1 OVERVIEW
User’s Manual U18172EJ3V0UD
18
1.5 Block Diagram
1.5.1
μ PD78F920x
78K0S
CPU
CORE
INTERNAL
HIGH-SPEED
RAM
FLASH
MEMORY
V SS
Note2
V DD
Note1
PORT 2
P20-P23
4
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
RESET CONTROL
SYSTEM
CONTROL
HIGH-SPEED
INTERNAL
OSCILLATOR
RESET/P34
X1/P23
X2/P22
16-bit TIMER/
EVENT COUNTER 00
TO00/TI010/P21
TI000/P20
TOH1/P20
8-bit TIMER H1
INTP0/P21
INTP1/P32
ANI0/P20-
ANI3/P23
4
A/D CONVERTER
INTERRUPT
CONTROL
PORT 3
P32
P34
PORT 4
P40, P43
2
LOW-SPEED
INTERNAL
OSCILLATOR
WATCHDOG TIMER
Notes 1. In
μ PD78F920x, VDD functions alternately as the A/D converter reference voltage input. When using the
A/D converter, stabilize V
DD at the supply voltage used (2.7 to 5.5 V).
2. In
μ PD78F920x, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect V
SS to a stabilized GND (= 0 V).