Datasheet

CHAPTER 11 STANDBY FUNCTION
User’s Manual U18172EJ3V0UD
195
(b) Release by reset signal generation
When the reset signal is input, STOP mode is released and a reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 11-6. STOP Mode Release by Reset signal generation
(1) If CPU clock is high-speed internal oscillation clock or external input clock
STOP
instruction
Reset signal
System clock
oscillation
Operation
mode
STOP mode
Reset
period
Operation mode
Oscillation Oscillation stops. Oscillation
CPU status
Operation
stops
Note
.
Note Operation is stopped (277
μ s (MIN.), 544 μ s (TYP.), 1.075 ms (MAX.)) because the option byte is
referenced.
(2) If CPU clock is crystal/ceramic oscillation clock (
μ PD78F920x only)
STOP
instruction
Reset signal
System clock
oscillation
Operation
mode
STOP mode
Reset
period
Operation
stops
Note
.
Operation
mode
Oscillation Oscillation stops. Oscillation
CPU status
Oscillation stabilization time
(2
10
/fX to 2
17
/fX)
Oscillation
stabilization waits
Note Operation is stopped (276 μ s (MIN.), 544 μ s (TYP.), 1.074 ms (MAX.)) because the option byte is
referenced.
Remark f
X: System clock oscillation frequency
Table 11-5. Operation in Response to Interrupt Request in STOP Mode
Release Source MK×× IE Operation
0 0 Next address instruction execution
0 1 Interrupt servicing execution
Maskable interrupt request
1
×
STOP mode held
Reset signal generation
− ×
Reset processing
×: don’t care
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