Datasheet

CHAPTER 11 STANDBY FUNCTION
User’s Manual U18172EJ3V0UD
191
(b) Release by reset signal generation
When the reset signal is input, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 11-3. HALT Mode Release by Reset Signal Generation
(1) When CPU clock is high-speed internal oscillation clock or external input clock
HALT
instruction
Reset signal
System clock
oscillation
Operation
mode
HALT mode
Reset
period Operation mode
Oscillates Oscillation stops Oscillates
CPU status
Operation
stops
Note
Note Operation is stopped (277
μ s (MIN.), 544 μ s (TYP.), 1.075 ms (MAX.)) because the option byte is
referenced.
(2) When CPU clock is crystal/ceramic oscillation clock (
μ PD78F920x only)
HALT
instruction
Reset signal
System clock
oscillation
Operation
mode
HALT mode
Reset
period
Operation
stops
Note
Oscillation
stabilization waits
Oscillates Oscillation stops Oscillates
CPU status
Oscillation stabilization time
(2
10
/f X to 2
17
/f X )
Operation
mode
Note Operation is stopped (276
μ s (MIN.), 544 μ s (TYP.), 1.074 ms (MAX.)) because the option byte is
referenced.
Remark f
X: System clock oscillation frequency
Table 11-3. Operation in Response to Interrupt Request in HALT Mode
Release Source MK×× IE Operation
0 0 Next address instruction execution
0 1 Interrupt servicing execution
Maskable interrupt request
1
×
HALT mode held
Reset signal generation
− ×
Reset processing
×: don’t care
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