Datasheet

CHAPTER 8 WATCHDOG TIMER
User’s Manual U18172EJ3V0UD
148
8.2 Configuration of Watchdog Timer
The watchdog timer consists of the following hardware.
Table 8-3. Configuration of Watchdog Timer
Item Configuration
Control registers
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Figure 8-1. Block Diagram of Watchdog Timer
Clock
input
controller
Output
controller
Internal reset signal
WDCS2
Internal bus
WDCS1 WDCS0WDCS3WDCS4
01 1
Selector
16-bit
counter
or
2
13
/fX to
2
20
/fX
Watchdog timer enable
register (WDTE)
Watchdog timer mode
register (WDTM)
3
2
Clear
Option byte
(to set “low-speed
internal oscillator cannot be
stopped” or “low-speed
internal oscillator can be
stopped by software”)
fRL/2
2
fX/2
4
2
11
/fRL to
2
18
/fRL
Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency
2. f
X: System clock oscillation frequency