Datasheet

User’s Manual U18172EJ3V0UD
146
CHAPTER 8 WATCHDOG TIMER
8.1 Functions of Watchdog Timer
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.
For details of RESF, see CHAPTER 12 RESET FUNCTION.
Table 8-1. Loop Detection Time of Watchdog Timer
Loop Detection Time
During Low-Speed Internal oscillation Clock Operation During System Clock Operation
2
11
/fRL (4.27 ms) 2
13
/fX (819.2 μ s)
2
12
/fRL (8.53 ms) 2
14
/fX (1.64 ms)
2
13
/fRL (17.07 ms) 2
15
/fX (3.28 ms)
2
14
/fRL (34.13 ms) 2
16
/fX (6.55 ms)
2
15
/fRL (68.27 ms) 2
17
/fX (13.11 ms)
2
16
/fRL (136.53 ms) 2
18
/fX (26.21 ms)
2
17
/fRL (273.07 ms) 2
19
/fX (52.43 ms)
2
18
/fRL (546.13 ms) 2
20
/fX (104.86 ms)
Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency
2. f
X: System clock oscillation frequency
3. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz.
The operation mode of the watchdog timer (WDT) is switched according to the option byte setting of the on-chip
low-speed internal oscillator as shown in Table 8-2.