Datasheet

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ( μ PD78F920x ONLY)
User’s Manual U18172EJ3V0UD
118
Figure 6-31. Configuration Diagram of PPG Output
16-bit timer capture/compare
register 000 (CR000)
16-bit timer counter 00
(TM00)
Clear
circuit
Noise
eliminator
f
XP
f XP
f XP /2
2
f XP /2
8
16-bit timer capture/compare
register 010 (CR010)
TO00/TI010/ANI1/
INTP0/P21
Selector
Output controller
TI000/ANI0/
TOH1/P20
Figure 6-32. PPG Output Operation Timing
t
0000H 0000H 0001H 0001H M − 1
Count clock
TM00 count value
TO00
Pulse width: (M + 1) × t
1 cycle: (N + 1) × t
N
CR000 capture value
CR010 capture value
M
M
N − 1
NN
ClearClear
Remark 0000H < M < N ≤ FFFFH