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User’s Manual 78K0S/KU1+ 8-Bit Single-Chip Microcontrollers μPD78F9200 μPD78F9500 μPD78F9201 μPD78F9501 Document No.
[MEMO] 2 User’s Manual U18172EJ3V0UD
NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
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INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the 78K0S/KU1+ in order to design and develop its application systems and programs. The target devices are the following subseries products. • 78K0S/KU1+: μPD78F9200, 78F9201, 78F9202, 78F9500, 78F9501, 78F9502 Purpose This manual is intended to give users on understanding of the functions described in the Organization below.
Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: ××× (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ... ×××× or ××××B Decimal ... ×××× Hexadecimal ... ××××H Related Documents The related documents indicated in this publication may include preliminary versions.
Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
CONTENTS CHAPTER 1 OVERVIEW.........................................................................................................................14 1.1 Features .........................................................................................................................................14 1.2 Ordering Information....................................................................................................................15 1.3 Pin Configuration (Top View) ...............................
3.3.4 Register addressing .......................................................................................................................... 46 3.4 Operand Address Addressing .................................................................................................... 47 3.4.1 Direct addressing .............................................................................................................................. 47 3.4.2 Short direct addressing ........................................
6.4.5 PPG output operations ....................................................................................................................116 6.4.6 One-shot pulse output operation .....................................................................................................119 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 ...............................................................124 CHAPTER 7 8-BIT TIMER H1 ..........................................................................
10.4.3 Interrupt request pending .............................................................................................................. 185 CHAPTER 11 STANDBY FUNCTION..................................................................................................186 11.1 Standby Function and Configuration .....................................................................................186 11.1.1 Standby function .................................................................................
16.6.3 RESET pin.....................................................................................................................................231 16.6.4 Port pins ........................................................................................................................................231 16.6.5 Power supply.................................................................................................................................231 16.
APPENDIX A DEVELOPMENT TOOLS ..............................................................................................310 A.1 Software Package ......................................................................................................................313 A.2 Language Processing Software ...............................................................................................313 A.3 Flash Memory Writing Tools................................................................................
CHAPTER 1 OVERVIEW 1.1 Features O 78K0S CPU core O ROM and RAM capacities Item Program Memory (Flash Memory) Memory (Internal High-Speed RAM) Part number μPD78F9200, 78F9500 1 KB μPD78F9201, 78F9501 2 KB μPD78F9202, 78F9502 4 KB 128 bytes O Minimum instruction execution time: 0.2 μs (with 10 MHz@4.0 to 5.
CHAPTER 1 OVERVIEW O Assembler and C language supported O Enhanced development environment • Support for full-function emulator (IECUBE), simplified emulator (MINICUBE2), and simulator O Supply voltage: VDD = 2.0 to 5.5 V ∗ Use these products at VDD = 2.2 to 5.5 V because the POC detection voltage (VPOC) is the supply voltage range. O Operating temperature range: TA = −40 to +85°C 1.
CHAPTER 1 OVERVIEW 1.3 Pin Configuration (Top View) 1.3.
CHAPTER 1 OVERVIEW 1.4 78K0S/Kx1+ Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number 78K0S/KU1+ 78K0S/KY1+ 78K0S/KA1+ 78K0S/KB1+ 10 pins 16 pins 20 pins 30/32 pins Item Number of pins Internal memory Flash memory 1 KB, 2 KB, 4 KB 2 KB 4 KB, 8 KB 4 KB, 8 KB 128 bytes 128 bytes 256 bytes 256 bytes RAM VDD = 2.0 to 5.5 V Supply voltage Note 1 0.20 μs (10 MHz, VDD = 4.0 to 5.5 V) 0.33 μs (6 MHz, VDD = 3.0 to 5.5 V) 0.40 μs (5 MHz, VDD = 2.
CHAPTER 1 OVERVIEW 1.5 Block Diagram 1.5.
CHAPTER 1 OVERVIEW 1.5.
CHAPTER 1 OVERVIEW 1.6 Functional Outline Item Internal memory μPD78F9200 μPD78F9201 μPD78F9202 μPD78F9500 μPD78F9501 μPD78F9502 Flash memory 1 KB High-speed RAM 128 bytes 2 KB Memory space 64 KB X1 input clock (oscillation frequency) • μPD78F920x 4 KB Crystal/ceramic/external clock input: 10 MHz (VDD = 2.0 to 5.5 V) • μPD78F950x External clock input: 10 MHz (VDD = 2.7 to 5.
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List 2.1.1 μPD78F920x (1) Port pins Pin Name I/O Function After Reset Alternate-Function Pin I/O P20 Port 2. Input 4-bit I/O port. P21 ANI1/TI010/ Can be set to input or output mode in 1-bit units. P22 Note 1 P23 Note 1 ANI0/TI000/TOH1 TO00/INTP0 An on-chip pull-up resistor can be connected by setting software. P32 I/O Port 3 Can be set to input or output mode in X2/ANI2 Note 1 X1/ANI3 Note 1 Input INTP1 Input RESET 1-bit units.
CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name I/O Function After Reset AlternateFunction Pin INTP0 Input External interrupt input for which the valid edge (rising edge, Input P21/ANI1/TI010/ TO00 falling edge, or both rising and falling edges) can be specified INTP1 P32 TI000 Input External count clock input to 16-bit timer/event counter 00.
CHAPTER 2 PIN FUNCTIONS 2.1.2 μPD78F950x (1) Port pins Pin Name I/O Function After Reset Alternate-Function Pin I/O P20 Port 2. Input port 4-bit I/O port. P21 TOH1 INTP0 Can be set to input or output mode in 1-bit units. P22 P23 − An on-chip pull-up resistor can be connected by setting Note software. P32 I/O EXCLK Port 3 Can be set to input or output mode in An on-chip pull-up 1-bit units.
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Functions 2.2.1 P20 to P23 (Port 2) P20 to P23 constitute a 4-bit I/O port. In addition to the function as I/O port pins, these pins also have a function to input an analog signal to the A/D converter, input/output a timer signal, and input an external interrupt request signal. P22 and P23 also function as the X2/ANI2 and X1/ANI3, respectively. For the setting method for pin functions, see CHAPTER 15 OPTION BYTE.
CHAPTER 2 PIN FUNCTIONS 2.2.2 P32 and P34 (Port 3) P32 is a 1-bit I/O port. In addition to the function as an I/O port pin, this pin also has a function to input an external interrupt request signal. P34 is a 1-bit input-only port. This pin is also used as a RESET pin, and when the power is turned on, this is the reset function. For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. When P34 in μPD78F920x is used as an input port pin, connect the pull-up resistor.
CHAPTER 2 PIN FUNCTIONS 2.2.6 EXCLK (μPD78F950x) This is the external clock input pin for the main system clock. EXCLK functions as P23. For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. Caution The P23/EXCLK pin is pulled down during reset. 2.2.7 VDD This is the positive power supply pin. In μPD78F920x, VDD functions alternately as the A/D converter reference voltage input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V). 2.2.
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Connection of Unused Pins Tables 2-1 and 2-2 show I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 2-1. Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins (μPD78F920x) Pin Name P20/ANI0/TI000/TOH1 I/O Circuit Type 11 I/O I/O Recommended Connection of Unused Pin Input: Individually connect to VDD or VSS via resistor. Output: Leave open.
CHAPTER 2 PIN FUNCTIONS Figure 2-1.
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The 78K0S/KU1+ can access up to 64 KB of memory space. Figures 3-1 to 3-3 show the memory maps. Figure 3-1.
CHAPTER 3 CPU ARCHITECTURE Figure 3-2.
CHAPTER 3 CPU ARCHITECTURE Figure 3-3.
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The 78K0S/KU1+ provide the following internal ROMs (or flash memory) containing the following capacities. Table 3-1.
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space 128-byte internal high-speed RAM is provided in the 78K0S/KU1+. The internal high-speed RAM can also be used as a stack memory. 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3). 3.1.4 Data memory addressing The 78K0S/KU1+ are provided with a wide range of addressing modes to make memory manipulation as efficient as possible.
CHAPTER 3 CPU ARCHITECTURE Figure 3-5.
CHAPTER 3 CPU ARCHITECTURE Figure 3-6.
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0S/KU1+ provide the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled. When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources.
CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area (Other than the internal high-speed RAM area cannot be set as the stack area). Figure 3-9.
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL). Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 3-12.
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register type.
CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously − FF00H, 7 6 5 4 3 2 1 0 − − − − − − − − 1 8 16 − − − − − − R/W √ √ − 00H 68 √ √ − 00H 68 page Address Reference Table 3-3.
CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF50H LVIM 7 6 5 4 3 2 1 0 F> LVIS1 LVIS0 ON> FF51H LVIS 0 0 0 0 LVIS3 LVIS2 R/W 1 8 16 √ √ − 00H page Address Reference Table 3-3.
CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FFA0H PFCMD FFA1H PFS FFA2H FLPMC FFA3H FLCMD FFA4H FLAPL FFA5H FLAPH FFA6H FLAPHC FFA7H FLAPLC FFA8H FLW − FFA9H to page Address Reference Table 3-3.
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions 7 0 PC CALL or BR PC+1 Low addr. PC+2 High addr. 15 8 7 0 PC 3.3.
CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed.
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed.
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 160-byte space FE80H to FF1FH (FE80H to FEFFH (internal high-speed RAM) + FF00H to FF1FH (special function registers)). The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area.
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH are accessed with short direct addressing.
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt request generation. Stack addressing can be used to access the internal high-speed RAM area only.
CHAPTER 4 PORT FUNCTIONS 4.1 Functions of Ports The 78K0S/KU1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1 shows the functions of each port. In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Functions P20 P40 P43 Port 4 Port 2 P23 P32 P34 Port 3 Table 4-1.
CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (μPD78F950x) Pin Name I/O Function After Reset AlternateFunction Pin P20 I/O P21 Input TOH1 INTP0 Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected by setting software. P22 P23 Port 2. 4-bit I/O port. − Note EXCLK P32 I/O Port 3. Can be set to input or output mode in 1- On-chip pull-up bit units.
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 2 (1) μPD78F920x Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 2 (PU2). This port can also be used for A/D converter analog input, timer I/O, and external interrupt request input.
CHAPTER 4 PORT FUNCTIONS Figure 4-2.
CHAPTER 4 PORT FUNCTIONS Figure 4-3.
CHAPTER 4 PORT FUNCTIONS Figure 4-4.
CHAPTER 4 PORT FUNCTIONS (2) μPD78F950x Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 2 (PU2). This port can also be used for timer I/O, and external interrupt request input. The P23 pin is also used as the EXCLK pin of the system clock oscillator.
CHAPTER 4 PORT FUNCTIONS Figure 4-5.
CHAPTER 4 PORT FUNCTIONS Figure 4-6.
CHAPTER 4 PORT FUNCTIONS Figure 4-7.
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 3 The P32 pin is a 1-bit I/O port with an output latch. This pin can be set to the input or output mode by using port mode register 3 (PM3). When this pin is used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3). This pin can also be used for external interrupt request input. The P32 pin is a Reset signal generation sets port 3 to the input mode. The P34 pin is a 1-bit input-only port.
CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P34 (μPD78F920x) Internal bus RD P34/RESET Reset Option byte RD: Read signal Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE.
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 4 Port 4 is a 2-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4) Note . When the P40 and P43 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 4 (PU4). Reset signal generation sets port 4 to the input mode. Figures 4-11 shows the block diagram of port 4.
CHAPTER 4 PORT FUNCTIONS (1) Port mode registers (PM2 to PM4) These registers are used to set the corresponding port to the input or output mode in 1-bit units. Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When a port pin is used as an alternate-function pin, set its port mode register and output latch as shown in Table 4-4.
CHAPTER 4 PORT FUNCTIONS (2) Port registers (P2 to P4) These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip. When a port register is read, the pin level is read in the input mode, and the value of the output latch of the port is read in the output mode. P20 to P23, P32, P40 and P43 are set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to 00H. Figure 4-13.
CHAPTER 4 PORT FUNCTIONS Figure 4-14. Format of Port Mode Control Register 2 (μPD78F920x only) Address: FF84H, After reset: R/W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n Specification of operation mode (n = 0 to 3) 0 Port/alternate-function (except the A/D converter function) mode 1 A/D converter mode Caution When PMC20 to PMC23 are set to 1, the port function on the P20/ANI0 to P23/ANI3 pins cannot be used.
CHAPTER 4 PORT FUNCTIONS (4) Pull-up resistor option registers (PU2 to PU4) These registers are used to specify whether an on-chip pull-up resistor is connected to P20 to P23, P32, P34, P40 and P43. By setting PU2 to PU4, an on-chip pull-up resistor can be connected to the port pin corresponding to the bit of PU2 to PU4. PU2 to PU4 are set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation set these registers to 00H. Figure 4-15.
CHAPTER 4 PORT FUNCTIONS 4.4 Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and outputs. 4.4.
CHAPTER 5 CLOCK GENERATORS 5.1 Functions of Clock Generators The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the watchdog timer and 8-bit timer H1 (TMH1). 5.1.1 System clock oscillators The following three types of system clock oscillators are used.
CHAPTER 5 CLOCK GENERATORS 5.2 Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1.
CHAPTER 5 CLOCK GENERATORS Figure 5-1.
CHAPTER 5 CLOCK GENERATORS Figure 5-1.
CHAPTER 5 CLOCK GENERATORS 5.3 Registers Controlling Clock Generators The clock generators are controlled by the following four registers.
CHAPTER 5 CLOCK GENERATORS The fastest instruction of the 78K0S/KU1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-2. Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Note 1 Minimum Instruction Execution Time: 2/fCPU High-speed internal oscillation clock (at 8.0 MHz (TYP.
CHAPTER 5 CLOCK GENERATORS (3) Oscillation stabilization time select register (OSTS) (μPD78F920x only) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the STOP mode is released.
CHAPTER 5 CLOCK GENERATORS 5.4 System Clock Oscillators The following three types of system clock oscillators are available. • High-speed internal oscillator: Internally oscillates a clock of 8 MHz (TYP.). • Crystal/ceramic oscillator Oscillates a clock of 2 MHz to 10 MHz. Note 1 • External clock input circuit: Notes 1. 2. 5.4.1 : Supplies a clock of 2 MHz to 10 MHz to the X1 pin Note 2 .
CHAPTER 5 CLOCK GENERATORS Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (b) Crossed signal lines PORT VSS X1 X2 VSS (c) Wiring near high fluctuating current X1 X2 (d) Current flowing through ground line of oscillator (Potential at points A, B, and C fluctuates.
CHAPTER 5 CLOCK GENERATORS Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched VSS 5.4.3 X1 X2 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin Note 1 . If external clock input is selected by the option byte as the system clock source, the X2 pin can be used as an I/O port pin. Note 2 For details of the option byte, refer to CHAPTER 15 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS.
CHAPTER 5 CLOCK GENERATORS 5.5 Operation of CPU Clock Generator A clock (fCPU) is supplied to the CPU from the system clock (fX) oscillated by one of the following three types of oscillators. • High-speed internal oscillator: Note 1 • Crystal/ceramic oscillator : Notes 1. 2. Oscillates a clock of 2 MHz to 10 MHz. Note 2 • External clock input circuit: Internally oscillates a clock of 8 MHz (TYP.). Supplies a clock of 2 MHz to 10 MHz to X1 pin .
CHAPTER 5 CLOCK GENERATORS (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then the high-speed internal oscillation clock operates as the system clock. Figure 5-9. Status Transition of Default Start by High-Speed internal oscillation Power application VDD > 2.1 V ±0.
CHAPTER 5 CLOCK GENERATORS (2) Crystal/ceramic oscillator (μPD78F920x only) If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 MHz to 10 MHz can be selected and the accuracy of processing is improved because the frequency deviation is small, as compared with highspeed internal oscillation (8 MHz (TYP.)). Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic oscillator. Figure 5-10.
CHAPTER 5 CLOCK GENERATORS Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation (μPD78F920x Only) Power application VDD > 2.1 V ±0.
CHAPTER 5 CLOCK GENERATORS (3) External clock input circuit If external clock input is selected by the option byte, the following is possible. • High-speed operation The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.)) because an oscillation frequency of 2 MHz to 10 MHz can be selected and an external clock with a small frequency deviation can be supplied.
CHAPTER 5 CLOCK GENERATORS Figure 5-13. Status Transition of Default Start by External Clock Input Power application VDD > 2.1 V ±0.
CHAPTER 5 CLOCK GENERATORS 5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. • Clock to peripheral hardware (fXP) • Low-speed internal oscillation clock (fRL) (1) Clock to peripheral hardware The clock to the peripheral hardware is supplied by dividing the system clock (fX). The division ratio is selected by the pre-processor clock control register (PPCC).
CHAPTER 5 CLOCK GENERATORS Figure 5-14. Status Transition of Low-Speed Internal Oscillator Power application VDD > 2.1 V ±0.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates interrupt requests at the preset time interval. • Number of counts: 2 to 65536 (2) External event counter 16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of valid level pulse width or more of a signal input externally.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Table 6-1.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. Figure 6-2.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) • When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 62). Table 6-2.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) (3) 16-bit timer capture/compare register 010 (CR010) CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00). CR010 is set by 16-bit memory manipulation instruction. Reset signal generation clears CR010 to 0000H. Figure 6-4.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Cautions 6. Changing the CR010 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. 6.3 Registers to Control 16-Bit Timer/Event Counter 00 The following seven types of registers are used to control 16-bit timer/event counter 00.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-5.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Remark TM00: 16-bit timer counter 00 CR000: 16-bit timer capture/compare register 000 CR010: 16-bit timer capture/compare register 010 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit capture/compare registers (CR000, CR010). CRC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of CRC00 to 00H. Figure 6-6.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot pulse output operation enable/disable, and output trigger of one-shot pulse by software. TOC00 is set by a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Caution 6. When the TOE00 is 0, set the TOE00, LVS00, and LVR00 at the same time with the 8-bit memory manipulation instruction. When the TOE00 is 1, the LVS00 and LVR00 can be set with the 1-bit memory manipulation instruction. (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid edges.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Cautions 3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. <1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled → If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-10. Format of Port Mode Control Register 2 (PMC2) Address: FF84H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n 6.4 Specification of operation mode (n = 0 to 3) 0 Port/Alternate-function (except A/D converter) mode 1 A/D converter mode Operation of 16-Bit Timer/Event Counter 00 6.4.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-11. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting “10” is prohibited.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-13.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is cleared to 0 and the interrupt request signal (INTTM000) is generated.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-16. External Event Counter Configuration Diagram Internal bus 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear fXP OVF00Note 16-bit timer counter 00 (TM00) Noise eliminator Valid edge of TI000 Note OVF00 is 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH. Figure 6-17.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-19.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-21. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock TM00 count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 TI000 pin input CR010 capture value D0 D1 D2 D3 INTTM010 (D1 − D0) × t (D2 − D1) × t Note (D3 − D2) × t Note The carry flag is set to 1. Ignore this setting.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-22. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 0 1 CR000 used as capture register Captures valid edge of TI010 pin to CR000.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock TM00 count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3 TI000 pin input CR010 capture value D0 D1 D2 INTTM010 TI010 pin input CR000 capture value D1 D2 + 1 INTTM000 (D1 − D0) × t (D2 − D1) × t Note (D3 − D2) × t ((D2 + 1) − D1) × t Note Note The carry flag is set to 1.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-24. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000Note.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-25. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H D0 D1 D0 + 1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3 TI000 pin input CR010 capture value D0 D2 CR000 capture value D1 D3 INTTM010 (D1 − D0) × t (D2 − D1) × t Note (D3 − D2) × t Note The carry flag is set to 1. Ignore this setting.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-26. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (2/2) (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting “11” is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting “10” is prohibited.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) 6.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-28 for the set value). <3> Set the TOC00 register (see Figure 6-28 for the set value). <4> Set any value to the CR000 register (0000H cannot be set). <5> Set the TMC00 register to start the operation (see Figure 6-28 for the set value).
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-28. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 0 0 0 0/1 0/1 1 1 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting “11” is prohibited). Does not invert output on match between TM00 and CR010. Disables one-shot pulse output.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) 6.4.5 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-30 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-30 for the set value). <2> Set any value to the CR000 register as the cycle.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-30. Control Register Settings for PPG Output Operation (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 × 0 0 CR000 used as compare register CR010 used as compare register (b) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 0 0 1 0/1 0/1 1 1 Enables TO00 output. Inverts output on match between TM00 and CR000.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-31. Configuration Diagram of PPG Output 16-bit timer capture/compare register 000 (CR000) Selector fXP fXP/22 fXP/28 Noise eliminator Output controller TI000/ANI0/ TOH1/P20 Clear circuit 16-bit timer counter 00 (TM00) fXP 16-bit timer capture/compare register 010 (CR010) Figure 6-32.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figures 6-33 and 6-35 for the set value). <3> Set the TOC00 register (see Figures 6-33 and 6-35 for the set value).
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-33. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) Prescaler mode register 00 (PRM00) PRM00 ES110 ES100 ES010 ES000 3 2 0/1 0/1 0/1 0/1 0 0 PRM001 PRM010 0/1 0/1 Selects count clock. Setting invalid (setting “10” is prohibited.) Setting invalid (setting “10” is prohibited.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-34. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 04H (TM00 count starts) Count clock TM00 count 0000H 0001H N N+1 0000H N−1 N M−1 M M+1 M+2 CR010 set value N N N N CR000 set value M M M M OSPT00 INTTM010 INTTM000 TO00 pin output Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC003 and TMC002 bits.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-35. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) Prescaler mode register 00 (PRM00) PRM00 ES110 ES100 ES010 ES000 3 2 0/1 0/1 0 1 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting “11” is prohibited). Specifies the rising edge for pulse width detection. Setting invalid (setting “10” is prohibited.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-36.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock. Figure 6-37.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) (4) Capture register data retention The values of 16-bit timer capture/compare registers 0n0 (CR0n0) after 16-bit timer/event counter 00 has stopped are not guaranteed. Remark n = 0, 1 (5) Setting of 16-bit timer mode control register 00 (TMC00) The timer operation must be stopped before writing to bits other than the OVF00 flag. (6) Setting of capture/compare control register 00 (CRC00) The timer operation must be stopped before setting CRC00.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) <3> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H. (12) One-shot pulse output with external trigger <1> Do not input the external trigger again while the one-shot pulse is output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. <2> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) Figure 6-39. Capture Register Data Retention Timing Count clock TM00 count value N N+1 N+2 M M+1 M+2 Edge input INTTM010 Capture read signal CR010 capture value X M+1 N+2 Capture Capture, but read value is not guaranteed (15) Capture operation <1> If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the TI000 pin.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) (17) Changing compare register during timer operation <1> With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare register, when changing CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the timing of the match, so the operation is not guaranteed in such cases.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) (18) Edge detection <1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. (a) Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled → If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (μPD78F920x ONLY) (23) External clock limitation <1> When using an input pulse of the TI000 pin as a count clock (external trigger), be sure to input the pulse width which satisfies the AC characteristics. For the AC characteristics, refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS. <2> When an external waveform is input to 16-bit timer/event counter 00, it is sampled by the noise limiter circuit and thus an error occurs on the timing to become valid inside the device.
CHAPTER 7 8-BIT TIMER H1 7.1 Functions of 8-Bit Timer H1 8-bit timer H1 has the following functions. • Interval timer • PWM output mode • Square-wave output 7.2 Configuration of 8-Bit Timer H1 8-bit timer H1 consists of the following hardware. Table 7-1.
132 Figure 7-1.
CHAPTER 7 8-BIT TIMER H1 (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-2. Format of 8-Bit Timer H Compare Register 01 (CMP01) Address: FF0EH Symbol 7 After reset: 00H 6 R/W 5 4 3 2 1 0 CMP01 Caution CMP01 cannot be rewritten during timer count operation.
CHAPTER 7 8-BIT TIMER H1 7.3 Registers Controlling 8-Bit Timer H1 The following four registers are used to control 8-Bit Timer H1. • 8-bit timer H mode register 1 (TMHMD1) • Port mode register 2 (PM2) • Port register 2 (P2) • Port mode control register 2 (PMC2) (μPD78F920x only) (1) 8-bit timer H mode register 1 (TMHMD1) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
CHAPTER 7 8-BIT TIMER H1 Figure 7-4.
CHAPTER 7 8-BIT TIMER H1 Note (2) Port mode register 2 (PM2) and port mode control register 2 (PMC2) When using the P20/TOH1/TI000/ANI0 pin for timer output, clear PM20, the output latch of P20, and PMC20 to 0. PM2 and PMC2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM2 to FFH, and clears PMC2 to 00H. Note μPD78F920x only Figure 7-5.
CHAPTER 7 8-BIT TIMER H1 (1) Usage Generates the INTTMH1 signal repeatedly at the same interval. <1> Set each register. Figure 7-7.
CHAPTER 7 8-BIT TIMER H1 Figure 7-8.
CHAPTER 7 8-BIT TIMER H1 Figure 7-8.
CHAPTER 7 8-BIT TIMER H1 7.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited. 8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register during timer operation is possible. The operation in PWM output mode is as follows.
CHAPTER 7 8-BIT TIMER H1 <4> When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. At this time, 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated. <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHE1 = 0.
CHAPTER 7 8-BIT TIMER H1 Figure 7-10. Operation Timing in PWM Output Mode (1/4) (a) Basic operation (00H < CMP11 < CMP01 < FFH) Count clock 8-bit timer counter H1 00H 01H A5H 00H 01H 02H CMP01 A5H CMP11 01H A5H 00H 01H 02H A5H 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <2> <3> <4> TOH1 (TOLEV1 = 1) <1> The count operation is enabled by setting the TMHE1 bit to 1. Start 8-bit timer counter H1 by masking one count clock to count up. At this time, TOH1 output remains inactive (when TOLEV1 = 0).
CHAPTER 7 8-BIT TIMER H1 Figure 7-10.
CHAPTER 7 8-BIT TIMER H1 Figure 7-10.
CHAPTER 7 8-BIT TIMER H1 Figure 7-10. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 = A5H) Count clock 8-bit timer counter H1 00H 01H 02H 80H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H A5H CMP01 02H (03H) 02H CMP11 <2> 03H <2>' TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHE1 = 1. Start 8-bit timer counter H1 by masking one count clock to count up.
CHAPTER 8 WATCHDOG TIMER 8.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 12 RESET FUNCTION. Table 8-1.
CHAPTER 8 WATCHDOG TIMER Table 8-2. Option Byte Setting and Watchdog Timer Operation Mode Option Byte Setting Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software Watchdog timer clock • Selectable by software (fX, fRL or stopped) Note 1 Fixed to fRL . • When reset is released: fRL source Operation after reset 18 Operation starts with the maximum interval (2 /fRL). Operation starts with the maximum interval 18 (2 /fRL).
CHAPTER 8 WATCHDOG TIMER 8.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 8-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 8-1.
CHAPTER 8 WATCHDOG TIMER 8.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer mode register (WDTM) • Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released.
CHAPTER 8 WATCHDOG TIMER Cautions 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. However, at the first write, if “1” and “x” are set for WDCS4 and WDCS3 respectively and the watchdog timer is stopped, then the internal reset signal does not occur even if the following are executed.
CHAPTER 8 WATCHDOG TIMER 8.4 8.4.1 Operation of Watchdog Timer Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to low-speed internal oscillation clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
CHAPTER 8 WATCHDOG TIMER Figure 8-4. Status Transition Diagram When “Low-Speed Internal Oscillator Cannot Be Stopped” Is Selected by Option Byte Reset WDT clock: fRL Overflow time: 546.13 ms (MAX.) WDTE = “ACH” Clear WDT counter. WDT clock is fixed to fRL. Select overflow time (settable only once). WDT clock: fRL Overflow time: 4.27 ms to 546.13 ms (MAX.) WDT count continues. HALT instruction STOP instruction Interrupt HALT WDT count continues. 152 Interrupt STOP WDT count continues.
CHAPTER 8 WATCHDOG TIMER 8.4.2 Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or system clock. After reset is released, operation is started at the maximum cycle of the low-speed internal oscillation clock (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
CHAPTER 8 WATCHDOG TIMER Figure 8-5. Status Transition Diagram When “Low-Speed Internal Oscillator Can Be Stopped by Software” Is Selected by Option Byte Reset WDT clock: fRL Overflow time: 546.13 ms (MAX.) WDCS4 = 1 WDT clock = fX Select overflow time (settable only once). WDTE = “ACH” Clear WDT counter. WDT clock = fRL Select overflow time (settable only once). WDT operation stops. WDTE = “ACH” Clear WDT counter. WDTE = “ACH” Clear WDT counter. LSRSTOP = 1 WDT clock: fRL Overflow time: 4.
CHAPTER 8 WATCHDOG TIMER 8.4.3 Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or low-speed internal oscillation clock is being used. (1) When the watchdog timer operation clock is the system clock (fX) when the STOP instruction is executed When STOP instruction is executed, operation of the watchdog timer is stopped.
CHAPTER 8 WATCHDOG TIMER (2) When the watchdog timer operation clock is the low-speed internal oscillation clock (fRL) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, operation stops for 34 μs (TYP.) and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 8-7.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) 9.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following function. • 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI3.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) Table 9-1. Sampling Time and A/D Conversion Time Reference Sampling Note 2 Voltage Time fXP = 8 MHz Conversion fXP = 10 MHz FR2 FR1 FR0 Note 3 Time RangeNote 1 Sampling Time Note 2 Conversion Sampling Note 3 Time Time Note 2 Conversion TimeNote 3 VDD ≥ 4.5 V 12/fXP 36/fXP 1.5 μs 4.5 μs 1.2 μs 3.6 μs 0 0 0 VDD ≥ 4.0 V 24/fXP 72/fXP 3.0 μs 9.0 μs 2.4 μs 7.2 μs 1 0 0 VDD ≥ 2.85 V 96/fXP 144/fXP 12.0 μs 18.0 μs 9.6 μs 14.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) Figure 9-2 shows the block diagram of A/D converter. Figure 9-2.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) (5) Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the D/A converter, and converts the result, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR).
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) 9.3 Registers Used by A/D Converter The A/D converter uses the following six registers.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) Figure 9-3.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) Notes 3. Set the sampling time as follows. 1.0 μs or more • VDD ≥ 4.5 V: • VDD ≥ 4.0 V: 2.4 μs or more • VDD ≥ 2.85 V: 3.0 μs or more • VDD ≥ 2.7 V: 11.0 μs or more 4. Set the A/D conversion time as follows. • VDD ≥ 4.5 V: 3.0 μs or more and less than 100 μs • VDD ≥ 4.0 V: 4.8 μs or more and less than 100 μs • VDD ≥ 2.85 V: 6.0 μs or more and less than 100 μs • VDD ≥ 2.7 V: 14.0 μs or more and less than 100 μs 5.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 9-5.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) (4) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit resolution result. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation makes ADCRH undefined. Figure 9-7.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) 9.4 9.4.1 A/D Converter Operations Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). <2> Set ADCE to 1 and wait for 1 μs or longer. <3> Execute two NOP instructions or an instruction equivalent to two machine cycles. <4> Set ADCS to 1 and start the conversion operation. (<5> to <11> are operations performed by hardware.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) Figure 9-10. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion Conversion result SAR Undefined ADCR, ADCRH Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) 9.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT ( VAIN VDD × 1024 + 0.5) or (ADCR − 0.5) × where, INT( ): VDD 1024 ≤ VAIN < (ADCR + 0.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) 9.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) The setting method is described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <3> Execute two NOP instructions or an instruction equivalent to two machine cycles. <4> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) 9.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) 9.6 Cautions for A/D Converter (1) Supply current in STOP mode To satisfy the DC characteristics of supply current in STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 before executing the STOP instruction. (2) Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) (5) ANI0/P20 to ANI3/P23 <1> The analog input pins (ANI0 to ANI3) are also used as I/O port pins (P20 to P23). When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access P20 to P23 while conversion is in progress; otherwise the conversion resolution may be degraded.
CHAPTER 9 A/D CONVERTER (μPD78F920x ONLY) (8) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 μs after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result.
CHAPTER 10 INTERRUPT FUNCTIONS 10.1 Interrupt Function Types There are two types of interrupts: maskable interrupts and resets. • Maskable interrupts These interrupts undergo mask control. When an interrupt request occurs, the standby release signal occurs, and if an interrupt can be acknowledged then the program corresponding to the address written in the vector table address is executed (vector interrupt servicing).
CHAPTER 10 INTERRUPT FUNCTIONS Table 10-1.
CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal (B) External maskable interrupt Internal bus External interrupt mode register (INTM0) Interrupt request Edge detector MK IE IF Vector table address generator Standby release signal IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag 10.
CHAPTER 10 INTERRUPT FUNCTIONS Table 10-2.
CHAPTER 10 INTERRUPT FUNCTIONS (2) Interrupt mask flag register 0 (MK0) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 is set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets MK0 to FFH. Figure 10-3.
CHAPTER 10 INTERRUPT FUNCTIONS Cautions 1. Be sure to clear bits 0, 1, 6, and 7 to 0. 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag (××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will enable interrupts.
CHAPTER 10 INTERRUPT FUNCTIONS A pending interrupt is acknowledged when a status in which it can be acknowledged is set. Figure 10-6 shows the algorithm of interrupt request acknowledgment. When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches.
CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-8. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) 8 clocks Clock CPU NOP MOV A, r Saving PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment processing starts after the next instruction is executed.
CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-9. Example of Multiple Interrupts (1/2) Example 1. Multiple interrupts are acknowledged INTxx servicing Main processing EI IE = 0 EI INTyy servicing IE = 0 INTyy INTxx RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated.
CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-9. Example of Multiple Interrupts (2/2) Example 3. A priority is controlled by the Multiple interrupts The vector interrupt enable state is set for INTP0, INTP1, and INTTMH1.
CHAPTER 11 STANDBY FUNCTION 11.1 Standby Function and Configuration 11.1.1 Standby function Table 11-1. Relationship Between Operation Clocks in Each Operation Status Status Low-Speed Internal Oscillator Note 1 Operation Mode Reset LSRSTOP = 0 Oscillating Oscillating Note 3 Hardware LSRSTOP = 1 Stopped Stopped Oscillating Oscillating Stopped HALT Notes 1.
CHAPTER 11 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
CHAPTER 11 STANDBY FUNCTION 11.1.2 Registers used during standby (μPD78F920x only) The oscillation stabilization time after the standby mode is released is controlled by the oscillation stabilization time select register (OSTS). Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATORS.
CHAPTER 11 STANDBY FUNCTION 11.2 Standby Function Operation 11.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operating statuses in the HALT mode are shown below. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag clear, the standby mode is immediately cleared if set. Table 11-2.
CHAPTER 11 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed. Figure 11-2.
CHAPTER 11 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 11-3.
CHAPTER 11 STANDBY FUNCTION 11.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
CHAPTER 11 STANDBY FUNCTION (2) STOP mode release Figure 11-4. Operation Timing When STOP Mode Is Released <1> If high-speed internal oscillation clock or external input clock is selected as system clock to be supplied STOP mode is released. STOP mode System clock oscillation CPU clock Operation stopsNote. High-speed internal oscillation clock or external clock input <2> If crystal/ceramic oscillation clock is selected as system clock to be supplied (μPD78F920x only) STOP mode is released.
CHAPTER 11 STANDBY FUNCTION (a) Release by unmasked interrupt request Note When an unmasked interrupt request (8-bit timer H1 , low-voltage detector, external interrupt request) is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Note Only when sets count clock to fRL/27 Figure 11-5.
CHAPTER 11 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 11-6. STOP Mode Release by Reset signal generation (1) If CPU clock is high-speed internal oscillation clock or external input clock STOP instruction Reset signal CPU status System clock oscillation Operation mode Oscillation Operation stopsNote.
CHAPTER 12 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer overflows (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
CHAPTER 12 RESET FUNCTION Figure 12-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF Reset signal of WDT Set LVIRF Set Clear Clear Reset signal to LVIM/LVIS register RESET Reset signal of POC Internal reset signal Reset signal of LVI Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit. Remarks 1. LVIM: Low-voltage detect register 2.
CHAPTER 12 RESET FUNCTION Figure 12-2. Timing of Reset by RESET Input <1> With high-speed internal oscillation clock or external clock input High-speed internal oscillation clock or external clock input CPU clock Normal operation in progress Reset period (oscillation stops) Normal operation (reset processing, CPU clock) RESET Operation stops because option byte is referencedNote. Internal reset signal Delay 100 ns (TYP.) Delay 100 ns (TYP.
CHAPTER 12 RESET FUNCTION Figure 12-3. Timing of Reset by Overflow of Watchdog Timer <1> With high-speed internal oscillation clock or external clock input High-speed internal oscillation clock or external clock input CPU clock Normal operation in progress Reset period (oscillation stops) Normal operation (reset processing, CPU clock) Operation stops because option byte is referencedNote. Watchdog overflow Internal reset signal Hi-Z Port pin The operation stop time is 277 μs (MIN.), 544 μs (TYP.
CHAPTER 12 RESET FUNCTION Figure 12-4. Reset Timing by RESET Input in STOP Mode <1> With high-speed internal oscillation clock or external clock input STOP instruction is executed. High-speed internal oscillation clock or external clock input CPU clock Normal operation in progress Stop status (oscillation stops) Reset period (oscillation stops) Normal operation (reset processing, CPU clock) RESET Operation stops because option byte is referencedNote. Internal reset signal Delay 100 ns (TYP.
CHAPTER 12 RESET FUNCTION Table 12-1. Hardware Statuses After Reset Acknowledgment (1/2) Hardware Note 1 Program counter (PC) Status After Reset Contents of reset vector table (0000H and 0001H) are set.
CHAPTER 12 RESET FUNCTION Table 12-1.
CHAPTER 12 RESET FUNCTION 12.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0S/KU1+. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset signal generation by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H. Figure 12-5.
CHAPTER 13 POWER-ON-CLEAR CIRCUIT 13.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (VDD) and detection voltage (VPOC = 2.1 V ±0.1 V), and generates internal reset signal when VDD < VPOC. • Compares supply voltage (VDD) and detection voltage (VPOC = 2.1 V ±0.1 V), and releases internal reset signal when VDD ≥ VPOC. Cautions 1.
CHAPTER 13 POWER-ON-CLEAR CIRCUIT 13.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 13-1. Figure 13-1. Block Diagram of Power-on-Clear Circuit VDD VDD + Internal reset signal − Reference voltage source 13.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC = 2.1 V ±0.
CHAPTER 13 POWER-ON-CLEAR CIRCUIT 13.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
CHAPTER 13 POWER-ON-CLEAR CIRCUIT Figure 13-3.
CHAPTER 14 LOW-VOLTAGE DETECTOR 14.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. • Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or internal reset signal when VDD < VLVI. • Detection levels (ten levels) of supply voltage can be changed by software. • Interrupt or reset function can be selected by software. • Operable in STOP mode.
CHAPTER 14 LOW-VOLTAGE DETECTOR 14.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detect register (LVIM) • Low-voltage detection level select register (LVIS) (1) Low-voltage detect register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00HNote 1. Figure 14-2.
CHAPTER 14 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00HNote. Figure 14-3.
CHAPTER 14 LOW-VOLTAGE DETECTOR 14.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. • Used as reset Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when VDD < VLVI, and releases internal reset when VDD ≥ VLVI. • Used as interrupt Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI) when VDD < VLVI. The operation is set as follows.
CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) <2> LVIMK flag (set by software) H Time <1> Note 1 LVION flag (set by software) Not cleared Not cleared <3> Clear <4> 0.
CHAPTER 14 LOW-VOLTAGE DETECTOR (2) When used as interrupt • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to instigate a wait of at least 0.2 ms. <5> Wait until “supply voltage (VDD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM is confirmed.
CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) Time <2> LVIMK flag (set by software) <1> Note 1 LVION flag (set by software) <7> Cleared by software <3> <4> 0.2 ms or longer LVIF flag <5> Note 2 INTLVI Note 2 LVIIF flag Note 2 <6> Cleared by software Internal reset signal Notes 1. 2. Remark 214 The LVIMK flag is set to “1” by reset signal generation.
CHAPTER 14 LOW-VOLTAGE DETECTOR 14.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. <1> When used as reset The system may be repeatedly reset and released from the reset status.
CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-6. Example of Software Processing After Release of Reset (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset ; Check reset source Note Initialization of ports Setting WDT Initialization processing <1> LVI reset ; The detection level is set with LVIS. The low-voltage detector is operated (LVION = 1) Setting LVI ; fXP = High-speed internal oscillation clock (8.4 MHz (MAX.
CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-6.
CHAPTER 15 OPTION BYTE 15.1 Functions of Option Byte The address 0080H of the flash memory of the 78K0S/KU1+ is an option byte area. When power is supplied or when starting after a reset, the option byte is automatically referenced, and settings for the specified functions are performed. When using the product, be sure to set the following functions by using the option byte. 15.1.
CHAPTER 15 OPTION BYTE 15.1.2 μPD78F950x (1) Selection of system clock source • High-speed internal oscillation clock • External clock input (2) Low-speed internal oscillation clock oscillation • Cannot be stopped. • Can be stopped by software. (3) Control of RESET pin • Used as RESET pin • RESET pin is used as an input-only port pin (P34) (see 15.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34)). • The on-chip pull-up resistor on RESET pin is selected, or RESET pin is set open.
CHAPTER 15 OPTION BYTE 15.2 Format of Option Byte Format of option bytes is shown below. 15.2.1 μPD78F920x Figure 15-3. Format of Option Byte (μPD78F920x) (1/2) Address: 0080H 7 6 5 4 3 2 1 0 1 DEFOSTS1 DEFOSTS0 1 RMCE OSCSEL1 OSCSEL0 LIOCP DEFOSTS1 DEFOSTS0 Oscillation stabilization time on power application or after reset release 0 0 2 /fx (102.4 μs) 0 1 2 /fx (409.6 μs) 1 0 2 /fx (3.27 ms) 1 1 2 /fx (13.
CHAPTER 15 OPTION BYTE Figure 15-3. Format of Option Byte (μPD78F920x) (2/2) LIOCP Low-speed internal oscillates 1 Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit) 0 Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit) Cautions 1. If it is selected that low-speed internal oscillator cannot be stopped, the count clock to the watchdog timer (WDT) is fixed to low-speed internal oscillation clock. 2.
CHAPTER 15 OPTION BYTE 15.2.2 μPD78F950x Figure 15-4. Format of Option Byte (μPD78F950x) (1/2) Address: 0080H 7 6 5 4 3 2 1 0 1 1 1 ENPU34 RMCE OSCSEL1 OSCSEL0 LIOCP ENPU34 Selection of on-chip pull-up resistor on RESET pin 1 On-chip pull-up resistor on RESET pin is selected. 0 On-chip pull-up resistor on RESET pin is not selected. Remark When used as RESET pin, the pin can be left open by setting ENPU34 to "1". RMCE Control of RESET pin 1 RESET pin is used as is.
CHAPTER 15 OPTION BYTE Figure 15-4. Format of Option Byte (μPD78F950x) (2/2) LIOCP Low-speed internal oscillates 1 Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit) 0 Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit) Cautions 1. If it is selected that low-speed internal oscillator cannot be stopped, the count clock to the watchdog timer (WDT) is fixed to low-speed internal oscillation clock. 2.
CHAPTER 16 FLASH MEMORY 16.1 Features The internal flash memory of the 78K0S/KU1+ has the following features.
CHAPTER 16 FLASH MEMORY 16.2 Memory Configuration The 1/2/4 KB internal flash memory area is divided into 4/8/16 blocks and can be programmed/erased in block units. All the blocks can also be erased at once, by using a dedicated flash memory programmer. Figure 16-1.
CHAPTER 16 FLASH MEMORY Table 16-1. Rewrite Method Rewrite Method On-board programming Off-board programming Functional Outline Flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash memory programmer. Operation Mode Flash memory programming mode Flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash memory programmer and a dedicated program adapter board (FA series).
CHAPTER 16 FLASH MEMORY 16.5 Programming Environment The environment required for writing a program to the flash memory is illustrated below. Figure 16-2. Environment for Writing Program to Flash Memory (FlashPro5/QB-MINI2) VDD FlashPro5 Host machine QB-MINI2 VSS RS-232-C RESET USB SO/TxD 78K0S/KU1+ Dedicated flash memory programmer CLK Remark For QB-MINI2, the name of the SO/TxD signal is DATA. A host machine that controls the dedicated flash memory programmer is necessary.
CHAPTER 16 FLASH MEMORY Table 16-2. Wiring Between 78K0S/KU1+ and FlashPro5/QB-MINI2 FlashPro5/QB-MINI2 Connection Pin Pin Name I/O 78K0S/KU1+ Connection Pin Pin Function Pin Name μPD78F920x CLK Output Clock to 78K0S/KU1+ X1/P23/ANI3 EXCLK/P23 SO/TxD Output Receive signal/on-board mode signal X2/P22/ANI2 P22 /RESET Output Reset signal RESET/P34 RESET/P34 VDD – VDD voltage generation/voltage monitor VDD VDD GND – Ground VSS VSS Figure 16-3.
CHAPTER 16 FLASH MEMORY 16.6 Processing of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset.
CHAPTER 16 FLASH MEMORY Figure 16-5. PG-FP5 Programming GUI Setting Example Set oscillation frequency Click (Standard tab in Device setup window) (Main window) Table 16-4. Oscillation Frequency and PG-FP5 Programming GUI Setting Value Example PG-FP5 GUI Software Setting Value Example Oscillation Frequency (Communication Frequency) 2 MHz ≤ fX < 4 MHz 8 MHz 4 MHz ≤ fX < 8 MHz 9 MHz 8 MHz ≤ fX < 9 MHz 10 MHz 9 MHz ≤ fX ≤ 10 MHz 8 MHz Caution The above values are recommended values.
CHAPTER 16 FLASH MEMORY 16.6.3 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed.
CHAPTER 16 FLASH MEMORY 16.7 On-Board and Off-Board Flash Memory Programming 16.7.1 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0S/KU1+ in the flash memory programming mode. When the 78K0S/KU1+ are connected to the flash memory programmer and a communication command is transmitted to the microcontroller, the microcontroller is set in the flash memory programming mode.
CHAPTER 16 FLASH MEMORY Table 16-6. Response Name Command Name Function ACK Acknowledges command/data. NAK Acknowledges illegal command/data. 16.7.3 Security settings The operations shown below can be prohibited using the security setting command. • Batch erase (chip erase) is prohibited Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is prohibited.
CHAPTER 16 FLASH MEMORY Table 16-8 shows the relationship between the security setting and the operation in each programming mode. Table 16-8. Relationship Between Security Setting and Operation In Each Programming Mode Programming Mode Security Setting On-Board/Off-Board Programming Security Setting Batch erase (chip erase) Possible Self Programming Security Operation Security Setting Note 1 Valid Security Operation Note 2 Impossible Invalid Block erase Write Notes 1.
Figure 16-8.
CHAPTER 16 FLASH MEMORY Figure 16-9. Self Programming State Transition Diagram User program Operation setting Normal mode Specific sequence Operation setting Self programming mode Self programming command completion/error Register for self programming Self programming command execution by HALT instruction Flash memory control block (hardware) Self programming command under execution Operation reference Flash memory Table 16-10.
CHAPTER 16 FLASH MEMORY 16.8.2 Cautions on self programming function • No instructions can be executed while a self programming command is being executed. Therefore, clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming. Refer to Table 16-10 for the time taken for the execution of self programming. • Interrupts that occur during self programming can be acknowledged after self programming mode ends.
CHAPTER 16 FLASH MEMORY This register is set with an 8-bit memory manipulation instruction. Reset signal generation makes the contents of this register undefined. Figure 16-10. Format of Flash Programming Mode Control Register (FLPMC) After reset: UndefinedNote 1 Address: FFA2H Symbol 7 FLPMC 0 6 4 3 2 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 FLSPM 0 5 R/WNote 2 1 0 0 FLSPM Selection of operation mode during self-programming mode Normal mode This is the normal operation status.
CHAPTER 16 FLASH MEMORY (2) Flash protect command register (PFCMD) If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an operation to write the flash programming mode control register (FLPMC) may have a serious effect on the system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop inadvertently. Writing FLPMC is enabled only when a write operation is performed in the following specific sequence.
CHAPTER 16 FLASH MEMORY Figure 16-12. Format of Flash Status Register (PFS) Address: FFA1H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PFS 0 0 0 0 0 WEPRERR VCERR FPRERR 1.
CHAPTER 16 FLASH MEMORY (4) Flash programming command register (FLCMD) This register is used to specify whether the flash memory is erased, written, or verified in the self-programming mode. This register is set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 16-13.
CHAPTER 16 FLASH MEMORY (5) Flash address pointers H and L (FLAPH and FLAPL) These registers are used to specify the start address of the flash memory when the memory is erased, written, or verified in the self-programming mode. FLAPH and FLAPL consist of counters, and they are incremented until the values match with those of FLAPHC and FLAPLC when the programming command is not executed. When the programming command is executed, therefore, set the value again.
CHAPTER 16 FLASH MEMORY (7) Flash write buffer register (FLW) This register is used to store the data to be written to the flash memory. This register is set with an 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 16-16.
CHAPTER 16 FLASH MEMORY Figure 16-17. Format of Protect Byte (2/2) • μ PD78F9202, 78F9502 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 Other than above Status Blocks 15 to 0 are protected. Blocks 13 to 0 are protected. Blocks 14 and 15 can be written or erased. Blocks 11 to 0 are protected. Blocks 12 to 15 can be written or erased. Blocks 9 to 0 are protected.
CHAPTER 16 FLASH MEMORY Figure 16-18. Example of Shifting to Self Programming Mode Shift to self programming mode <1> Disable interrupts (by setting MK0 to FFH and executing DI instruction) ; When interrupt function is used <2> Clear FLCMD (FLCMD=00H).
CHAPTER 16 FLASH MEMORY An example of the program that shifts the mode to self programming mode is shown below.
CHAPTER 16 FLASH MEMORY 16.8.5 Example of shifting self programming mode to normal mode The operating mode must be returned from self programming mode to normal mode after performing self programming. An example of shifting to normal mode is explained below. <1> Clear FLCMD (FLCMD=00H). <2> Clear the flash status register (PFS). <3> Set normal mode using a specific sequence. • Write the specific value (A5H) to PFCMD.
CHAPTER 16 FLASH MEMORY Figure 16-19.
CHAPTER 16 FLASH MEMORY An example of a program that shifts the mode to normal mode is shown below.
CHAPTER 16 FLASH MEMORY 16.8.6 Example of block erase operation in self programming mode An example of the block erase operation in self programming mode is explained below. <1> Set 03H (block erase) to the flash program command register (FLCMD). <2> Set the block number to be erased, to flash address pointer H (FLAPH). <3> Set flash address pointer L (FLAPL) to 00H. <4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC).
CHAPTER 16 FLASH MEMORY Figure 16-20. Example of Block Erase Operation in Self Programming Mode Block erasure <1> Set erase command (FLCMD = 03H) <2> Set no. of block to be erased to FLAPH <3> Set FLAPL to 00H <4> Set the same value as that of FLAPH to FLAPHC <5> Set FLAPLC to 00H <6> Clear PFS <7> Clear & restart WDT counter (WDTE = ACH)Note <8> Execute HALT instruction <9> Check execution result Abnormal The erase command can be re-executed.
CHAPTER 16 FLASH MEMORY An example of a program that performs a block erase in self programming mode is shown below. ;---------------------------;START ;---------------------------- MOV B,#48 ; Specifies the number of times the erase command can be ; executed. ; (4.0 V to 5.
CHAPTER 16 FLASH MEMORY 16.8.7 Example of block blank check operation in self programming mode An example of the block blank check operation in self programming mode is explained below. <1> Set 04H (block blank check) to the flash program command register (FLCMD). <2> Set the number of block for which a blank check is performed, to flash address pointer H (FLAPH). <3> Set flash address pointer L (FLAPL) to 00H. <4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC).
CHAPTER 16 FLASH MEMORY Figure 16-21. Example of Block Blank Check Operation in Self Programming Mode Block blank check <1> Set block blank check command (FLCMD = 04H) <2> Set no.
CHAPTER 16 FLASH MEMORY An example of a program that performs a block blank check in self programming mode is shown below.
CHAPTER 16 FLASH MEMORY 16.8.8 Example of byte write operation in self programming mode An example of the byte write operation in self programming mode is explained below. <1> Set 05H (byte write) to the flash program command register (FLCMD). <2> Set the number of block to which data is to be written, to flash address pointer H (FLAPH). <3> Set the address at which data is to be written, to flash address pointer L (FLAPL). <4> Set the data to be written, to the flash write buffer register (FLW).
CHAPTER 16 FLASH MEMORY Figure 16-22. Example of Byte Write Operation in Self Programming Mode Byte write <1> Set byte write command (FLCMD = 05H) <2> Set no.
CHAPTER 16 FLASH MEMORY An example of a program that performs a byte write in self programming mode is shown below.
CHAPTER 16 FLASH MEMORY 16.8.9 Example of internal verify operation in self programming mode An example of the internal verify operation in self programming mode is explained below. • Internal verify 1 <1> Set 01H (internal verify 1) to the flash program command register (FLCMD). <2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH). <3> Sets the flash address pointer L (FLAPL) to 00H.
CHAPTER 16 FLASH MEMORY Figure 16-23. Example of Internal Verify 1 Operation in Self Programming Mode Internal verify 1 <1> Set internal verify 1 command (FLCMD = 01H) <2> Set No.
CHAPTER 16 FLASH MEMORY Figure 16-24. Example of Internal Verify 2 Operation in Self Programming Mode Internal verify 2 <1> Set internal verify 2 command (FLCMD = 02H) <2> Set No.
CHAPTER 16 FLASH MEMORY An example of a program that performs an internal verify in self programming mode is shown below.
CHAPTER 16 FLASH MEMORY 16.8.10 Examples of operation when command execution time should be minimized in self programming mode Examples of operation when the command execution time should be minimized in self programming mode are explained below. (1) Erasure to blank check <1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <2> Execution of block erase → Error check (<1> to <12> in 16.8.6) <3> Execution of block blank check → Error check (<1> to <11> in 16.8.
CHAPTER 16 FLASH MEMORY An example of a program when the command execution time (from erasure to black check) should be minimized in self programming mode is shown below.
CHAPTER 16 FLASH MEMORY MOV FLAPLC,#0FFH ; Fixes FLAPLC to “FFH” MOV WDTE,#0ACH ; Clears & restarts WDT HALT MOV ; Self programming is started A,PFS CMP A,#00H BNZ $StatusError ; Checks blank check error ; Performs abnormal termination processing when an error ; occurs.
CHAPTER 16 FLASH MEMORY (2) Write to internal verify <1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <2> Specification of source data for write <3> Execution of byte write → Error check (<1> to <10> in 16.8.8) <4> <3> is repeated until all data are written. <5> Execution of internal verify → Error check (<1> to <11> in 16.8.9) <6> Mode is shifted from self programming mode to normal mode (<1> to <6> in 16.8.5) Figure 16-26.
CHAPTER 16 FLASH MEMORY An example of a program when the command execution time (from write to internal verify) should be minimized in self programming mode is shown below.
CHAPTER 16 FLASH MEMORY INCW DE BR FlashWriteLoop ; Address at which data is to be written + 1 FlashVerify: MOVW HL,#WriteAdr ; Sets verify address MOV FLCMD,#02H ; Sets flash control command (internal verify 2) MOV A,H MOV FLAPH,A MOV A,L MOV FLAPL,A MOV A,D MOV FLAPHC,A MOV A,E MOV FLAPLC,A ; Sets verify end address MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Sets verify start address ; Sets verify start address ; Sets verify end address ; Self programming is started
CHAPTER 16 FLASH MEMORY ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: ;--------------------------------------------------------------------; Data to be written ;--------------------------------------------------------------------DataAdrTop: DB XXH DB XXH DB XXH DB XXH : : DB XXH DataAdrBtm: ;---------------------------------------------------------------
CHAPTER 16 FLASH MEMORY Figure 16-27.
CHAPTER 16 FLASH MEMORY An example of a program when the interrupt-disabled time (from erasure to blank check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------;START ;--------------------------------------------------------------------- MOV B,#48 ; Specifies the number of times the erase command can be ; executed. ; (4.0 V to 5.
CHAPTER 16 FLASH MEMORY CMP A,#00H BNZ $StatusError ; Checks blank check error ; Performs abnormal termination processing when an error occurs CALL !ModeOff BR StatusNormal ; Shift to normal mode RetryCheck: DBNZ B,$EraseRetry ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------Status
CHAPTER 16 FLASH MEMORY ;--------------------------------------------------------------------; Processing to shift to normal mode ;--------------------------------------------------------------------ModeOffLoop: MOV FLCMD,#00H ; Clears FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC
CHAPTER 16 FLASH MEMORY (2) Write to internal verify <1> Specification of source data for write <2> Specification of byte write command (<1> to <4> in 16.8.8) <3> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <4> Execution of byte write command → Error check (<5> to <10> in 16.8.8) <5> Mode is shifted from self programming mode to normal mode (<1> to <6> in 16.8.5) <6> <2> to <5> is repeated until all data are written.
CHAPTER 16 FLASH MEMORY Figure 16-28.
CHAPTER 16 FLASH MEMORY An example of a program when the interrupt-disabled time (from write to internal verify) should be minimized in self programming mode is shown below.
CHAPTER 16 FLASH MEMORY FlashVerify: MOVW HL,#WriteAdr ; Sets verify address MOV FLCMD,#02H ; Sets flash control command (internal verify 2) MOV A,H MOV FLAPH,A MOV A,L MOV FLAPL,A MOV A,D MOV FLAPHC,A ; Sets verify start address ; Sets verify start address ; Sets verify end address MOV A,E MOV FLAPLC,A ; Sets verify end address CALL !ModeOn ; Shift to self programming mode ; Execution of internal verify command MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ;
CHAPTER 16 FLASH MEMORY DI ; Configure settings so that the CPU clock ≥ 1 MHz ModeOnLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode via FLPMC register control (sets ; value) NOP HALT BT PFS.
CHAPTER 16 FLASH MEMORY DB XXH : : DB XXH DataAdrBtm: ;--------------------------------------------------------------------- Remark Internal verify 2 is used in the above program example. Use internal verify 1 to verify s whole block.
CHAPTER 17 ON-CHIP DEBUG FUNCTION 17.1 Connecting QB-MINI2 to 78K0S/KU1+ Note 1 The 78K0S/KU1+ uses RESET, X1 , X2 Note 2 , INTP1, VDD, and GND pins to communicate with the host machine via an on-chip debug emulator (QB-MINI2). Notes 1. μPD78F920x: X1/P23/ANI3, μPD78F950x: EXCLK/P23 Caution The 78K0S/KU1+ has an on-chip debug function, which is provided for development and 2. μPD78F920x: X2/P22/ANI2, μPD78F950x: P22 evaluation.
CHAPTER 17 ON-CHIP DEBUG FUNCTION Notes 2. This is the pin connection when the X1 and X2 pins are not used in the target system. When using the X1 and X2 pins, refer to 17.1.2 Connection of X1 and X2 pins. 3. No problem will occur if the dashed line portions are connected. 4. This pin is connected to enhance the accuracy of time measurement between run and break during debugging. Debugging is possible even if this pin is left open, but measurement error occurs in several ms units. 5.
CHAPTER 17 ON-CHIP DEBUG FUNCTION Figure 17-4.
CHAPTER 17 ON-CHIP DEBUG FUNCTION 17.2 Securing of user resources The user must prepare the following to perform communication between QB-MINI2 and the target device and implement each debug function. For details of the setting, refer to QB-MINI2 User’s Manual (U18371E). • Securement of memory space The shaded portions in Figure 17-6 are the areas reserved for placing the debug monitor program, so user programs cannot be allocated in these spaces. Figure 17-6.
CHAPTER 18 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the 78K0S/KU1+. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 18.1 Operation 18.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details).
CHAPTER 18 INSTRUCTION SET OVERVIEW 18.1.
CHAPTER 18 INSTRUCTION SET OVERVIEW 18.
CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z MOVW rp, #word 3 6 rp ← word AX, saddrp 2 6 AX ← (saddrp) AC CY 2 8 (saddrp) ← AX AX, rp Note 1 4 AX ← rp rp, AX Note 1 4 rp ← AX XCHW AX, rp Note 1 8 AX ↔ rp ADD A, #byte 2 4 A, CY ← A + byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte × × × A, r 2 4 A, CY ← A + r × × × A, saddr 2 4 A, CY ← A + (saddr) × × × A, !addr16 3 8 A, CY ← A + (addr16) × ×
CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z SUBC AND OR XOR Remark A, #byte 2 4 A, CY ← A − byte − CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) − byte − CY × × × A, r 2 4 A, CY ← A − r − CY × × × A, saddr 2 4 A, CY ← A − (saddr) − CY × × × A, !addr16 3 8 A, CY ← A − (addr16) − CY × × × A, [HL] 1 6 A, CY ← A − (HL) − CY × × × A, [HL + byte] 2 6 A, CY ← A − (HL + byte) − CY × × × A, #byte 2 4 A ← A ∧ byte
CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z AC CY A, #byte 2 4 A − byte × × × saddr, #byte 3 6 (saddr) − byte × × × A, r 2 4 A−r × × × A, saddr 2 4 A − (saddr) × × × A, !addr16 3 8 A − (addr16) × × × A, [HL] 1 6 A − (HL) × × × A, [HL + byte] 2 6 A − (HL + byte) × × × ADDW AX, #word 3 6 AX, CY ← AX + word × × × SUBW AX, #word 3 6 AX, CY ← AX − word × × × CMPW AX, #word 3 6 AX − word × × × I
CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z CALL !addr16 3 6 (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L, PC ← addr16, SP ← SP − 2 CALLT [addr5] 1 8 (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L, PCH ← (00000000, addr5 + 1), PCL ← (00000000, addr5), SP ← SP − 2 RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2 RETI 1 8 PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0 PSW 1 2 (SP − 1) ← PSW, SP ← SP − 1 rp 1 4 (SP − 1) ← rpH, (
CHAPTER 18 INSTRUCTION SET OVERVIEW 18.
CHAPTER 18 INSTRUCTION SET OVERVIEW (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word AX rp Note saddrp SP None 1st Operand AX rp ADDW SUBW MOVW CMPW XCHW MOVW MOVW MOVW Note MOVW INCW DECW PUSH POP saddrp MOVW sp MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand $addr16 None 1st Operand A.bit sfr.bit saddr.bit PSW.
CHAPTER 18 INSTRUCTION SET OVERVIEW (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand AX !addr16 [addr5] $addr16 1st Operand Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U18172EJ3V0UD 293
CHAPTER 19 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Symbol Supply voltage Input voltage Analog input voltage Output current, high Output current, low Operating ambient Ratings Unit VDD −0.3 to +6.5 V VSS −0.3 to +0.3 Note 2 −0.3 to VDD + 0.3 V VO −0.3 to VDD + 0.3 Note 1 V VAN −0.3 to VDD + 0.3 Note 1 V IOH IOL TA temperature Notes 1. 2. P20 to P23, P32, P34, P40, P43 Per pin −10.0 mA Total of P20 to P23, P32, P40, P43 −44.
CHAPTER 19 ELECTRICAL SPECIFICATIONS X1 Oscillator Characteristics (1) μPD78F920x (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Resonator Recommended Circuit VSS X1 Ceramic X2 Parameter Conditions Oscillation MIN. TYP. MAX. Unit 2.0 10.0 MHz 2.0 10.0 MHz MHz Note 2 frequency (fX) resonator C1 C2 VSS X1 Crystal X2 Oscillation Note 2 frequency (fX) resonator C1 External C2 X1 2.7 V ≤ VDD ≤ 5.5 V 2.0 10.0 frequency (fX) 2.0 V ≤ VDD < 2.7 V 2.0 5.
CHAPTER 19 ELECTRICAL SPECIFICATIONS High-Speed Internal Oscillator Characteristics (1) μPD78F920x (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Resonator Parameter Conditions High-speed internal Oscillation frequency (fX = 8 oscillator MHz 2.7 V ≤ VDD ≤ 5.5 V Note 2 ) deviation Oscillation frequency (fX) Notes 1. MAX. Unit TA = −10 to +70°C ±3 % TA = −40 to +85°C ±5 % 2.0 V ≤ VDD < 2.7 V Note 2 MIN. TYP. 5.5 MHz Use this product in a voltage range of 2.2 to 5.
CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (1/4) (1) μPD78F920x (TA = −40 to +85°C, VDD = 2.0 to 5.5 V Note, VSS = 0 V) (1/2) Parameter Output current, high Output current, low Input voltage, high Symbol IOH IOL VIH1 Conditions MIN. TYP. MAX. Unit Per pin 2.0 V ≤ VDD ≤ 5.5 V –5 mA Total of all pins 4.0 V ≤ VDD ≤ 5.5 V –25 mA 2.0 V ≤ VDD < 4.0 V –15 mA Per pin 2.0 V ≤ VDD ≤ 5.5 V 10 mA Total of all pins 4.0 V ≤ VDD ≤ 5.5 V 30 mA 2.0 V ≤ VDD < 4.0 V 15 mA 0.
CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (2/4) (1) μPD78F920x (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) (2/2) Parameter Note 3 Supply current Symbol IDD1 Note 2 Conditions MIN. TYP. MAX. Unit Crystal/ceramic fX = 10 MHz When A/D converter is stopped 6.1 12.2 oscillation, VDD = 5.0 V ±10% When A/D converter is operating 7.6 15.2 fX = 6 MHz When A/D converter is stopped 5.5 11.0 external clock input oscillation operating mode mA Note 4 Note 6 VDD = 5.
CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (3/4) (2) μPD78F950x (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote, VSS = 0 V) (1/2) Parameter Output current, high Output current, low Symbol IOH IOL Conditions MIN. TYP. MAX. Unit Per pin 2.0 V ≤ VDD ≤ 5.5 V –5 mA Total of all pins 4.0 V ≤ VDD ≤ 5.5 V –25 mA 2.0 V ≤ VDD < 4.0 V –15 mA Per pin 2.0 V ≤ VDD ≤ 5.5 V 10 mA Total of all pins 4.0 V ≤ VDD ≤ 5.5 V 30 mA 2.0 V ≤ VDD < 4.0 V 15 mA Input voltage, high VIH1 0.
CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (4/4) (2) μPD78F950x (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) (2/2) Parameter Note 3 Supply current Symbol IDD1 Note 2 Conditions External clock fX = 10 MHz input oscillation VDD = 5.0 V ±10% operating mode MIN. TYP. MAX. Unit fX = 6 MHz Note 6 6.1 12.2 mA 5.5 11.0 mA 3.0 6.0 mA 1.7 3.8 mA Note 4 VDD = 5.0 V ±10% Note 4 fX = 5 MHz VDD = 3.
CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Characteristics Basic operation (TA = −40 to +85°C, VDD = 2.0 to 5.5 V Parameter Symbol Cycle time (minimum TCY tINTH, width, low-level width tINTL RESET input low-level tRSL MAX. Unit 16 μs 3.0 V ≤ VDD < 4.0 V 0.33 16 μs 2.7 V ≤ VDD < 3.0 V 0.4 16 μs 2.0 V ≤ VDD < 2.7 V 1 16 μs High-speed internal 4.0 V ≤ VDD ≤ 5.5 V 0.23 4.22 μs oscillation clock 2.7 V ≤ VDD < 4.0 V 0.47 4.22 μs 2.0 V ≤ VDD < 2.7 V 0.95 4.22 μs 4.
CHAPTER 19 ELECTRICAL SPECIFICATIONS Note TCY vs. VDD (Crystal/Ceramic Oscillation Clock , External Clock Input) 60 16 Cycle time TCY [μs] 10 Guaranteed operation range 1.0 0.4 0.33 0.1 1 2 2.7 3 4 5 5.5 6 Supply voltage VDD [V] Note μPD78F920x only TCY vs. VDD (High-speed internal oscillator Clock) 60 Cycle time TCY [μs] 10 4.22 Guaranteed operation range 1.0 0.95 0.47 0.23 0.1 1 302 2 3 4 5 6 2.7 5.
CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.
CHAPTER 19 ELECTRICAL SPECIFICATIONS A/D Converter Characteristics (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 VNote 1, VSS = 0 VNote 2) (μPD78F920x only) (1) A/D converter basic characteristics Parameter Symbol Conditions Resolution Conversion time tCONV Analog input voltage MIN. TYP. MAX. Unit 10 10 10 bit 4.5 V ≤ VDD ≤ 5.5 V 3.0 100 μs 4.0 V ≤ VDD < 4.5 V 4.8 100 μs 2.85 V ≤ VDD < 4.0 V 6.0 100 μs 2.7 V ≤ VDD < 2.85 V 14.
CHAPTER 19 ELECTRICAL SPECIFICATIONS POC Circuit Characteristics (TA = −40 to +85°C) Parameter Symbol Conditions VPOC Detection voltage MIN. TYP. MAX. Unit 2.0 2.1 2.2 V μs tPTH VDD: 0 V → 2.1 V Response delay time 1 Note 1 tPTHD When power supply rises, after reaching detection voltage (MAX.) 3.0 ms Response delay time 2 Note 2 tPD When power supply falls 1.0 ms Power supply rise time Minimum pulse width 1.5 tPW 0.2 ms Notes 1.
CHAPTER 19 ELECTRICAL SPECIFICATIONS LVI Circuit Characteristics (TA = −40 to +85°C) Parameter Symbol Detection voltage Note 1 Response time TYP. MAX. Unit VLVI0 4.1 4.3 4.5 V VLVI1 3.9 4.1 4.3 V VLVI2 3.7 3.9 4.1 V VLVI3 3.5 3.7 3.9 V VLVI4 3.3 3.5 3.7 V VLVI5 3.15 3.3 3.45 V VLVI6 2.95 3.1 3.25 V VLVI7 2.7 2.85 3.0 V VLVI8 2.5 2.6 2.7 V VLVI9 2.25 2.35 2.45 V 0.2 2.0 ms tLW Operation stabilization wait time 2. MIN.
CHAPTER 19 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics (TA = –40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Supply current Note 1 Erasure count Symbol Conditions IDD VDD = 5.5 V NERASE TA = −40 to +85°C MIN. TYP. MAX. Unit 7.0 mA 1000 Times (per 1 block) Chip erase time Block erase time TCERASE TBERASE TA = −10 to +85°C, 4.5 V ≤ VDD ≤ 5.5 V 0.8 s NERASE ≤ 100 3.5 V ≤ VDD < 4.5 V 1.0 s 2.7 V ≤ VDD < 3.5 V 1.2 s TA = −10 to +85°C, 4.
CHAPTER 20 PACKAGE DRAWING 10-PIN PLASTIC SSOP (5.72 mm (225)) V 10 detail of lead end 6 T I P 5 1 L U V A W W F H G J S E B C K N S D M M (UNIT:mm) ITEM A B 3.60± 0.10 0.50 C 0.65 (T.P.) NOTE D 0.24 ± 0.08 Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. E 0.10±0.05 F 1.45 MAX. G 1.20 ± 0.10 H 6.40± 0.20 I 4.40±0.10 J K 1.00±0.20 + 0.08 0.17 0.07 L 0.50 M 0.13 N T 0.10 + 5° 3° 3° 0.25 (T.P.) U 0.60±0.
CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Caution For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 21-1.
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the 78K0S/KU1+. Figure A-1 shows the development tool configuration.
APPENDIX A DEVELOPMENT TOOLS Figure A-1.
APPENDIX A DEVELOPMENT TOOLS Figure A-1.
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package Development tools (software) common to the 78K0S microcontrollers are combined in this package. SP78K0S 78K0S microcontroller software package A.2 Language Processing Software RA78K0S Note 1 This assembler converts programs written in mnemonics into object codes executable with a Assembler package microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization.
APPENDIX A DEVELOPMENT TOOLS A.3 Flash Memory Writing Tools A.3.1 When using flash memory programmer PG-FP5 and FL-PR5 FL-PR5, PG-FP5 This is a flash memory programmer dedicated to microcontrollers incorporating a flash Flash memory programmer memory. FA-78F9202MA-CAC-RX Flash memory writing adapter This is a flash memory writing adapter which is used in connection with the flash memory programmer. Remarks 1. FL-PR5 and FA-78F9202MA-CAC-RX are products of Naito Densei Machida Mfg. Co.
APPENDIX A DEVELOPMENT TOOLS Remarks 1. The QB-78K0SKX1 is supplied with the integrated debugger ID78K0S-QB, a USB interface cable, the on-chip debug emulator QB-MINI2, and a connection cable. Download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/en/ods/) when using the QB-MINI2. 2. The packed contents of QB-78K0SKX1 differ depending on the part number, as follows.
APPENDIX B NOTES ON DESIGNING TARGET SYSTEM This chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the QB-78K0SKX1 is used. For the package drawings of the target connector, exchange adapter, and emulation probe, see the following website. http://www.necel.com/micro/en/development/asia/iecube/outline_QB.html Figure B-1.
APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. When using the 78K0S/Kx1+ target cable (single track) Top view Unit : mm 2.54 2.54 : A interval pin header → More than 2.54mm : A contact area of a pin header → 0.635 × 0.
APPENDIX C REGISTER INDEX C.
APPENDIX C REGISTER INDEX [P] Port mode control register 2 (PMC2) … 68, 100, 136, 165 Port mode register 2 (PM2) … 67, 100, 136, 165 Port mode register 3 (PM3) … 67 Port mode register 4 (PM4) … 67 Port register 2 (P2) … 68 Port register 3 (P3) … 68 Port register 4 (P4) … 68 Preprocessor clock control register (PPCC) … 76 Prescaler mode register 00 (PRM00) … 99 Processor clock control register (PCC) … 76 Pull-up resistor option register 2 (PU2) … 70 Pull-up resistor option register 3 (PU3) … 70 Pull-up resi
APPENDIX C REGISTER INDEX C.
APPENDIX C REGISTER INDEX [P] P2: Port register 2 … 68 P3: Port register 3 … 68 P4: Port register 4 … 68 PCC: Processor clock control register … 76 PFCMD: Flash protect command register … 239 PFS: Flash status register … 239 PM2: Port mode register 2 … 67, 100, 136, 165 PM3: Port mode register 3 … 67 PM4: Port mode register 4 … 67 PMC2: Port mode control register 2 … 68, 100, 136, 165 PPCC: Preprocessor clock control register … 76 PRM00: Prescaler mode register 00 … 99 PU2: Pull-up
APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document. “Classification (hard/soft)” in table is as follows.
APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 4 Chapter (2/15) Function Port functions Details of Function Cautions Page P21, P32 Because P21 and P32 are also used as external interrupt pins, the corresponding p. 67 interrupt request flag is set if each of these pins is set to the output mode and its output level is changed. To use the port pin in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance.
APPENDIX D LIST OF CAUTIONS Soft Classification Hard Chapter 6 Chapter (3/15) Function 16-bit timer/ event counters 00 Details of Function CR000: 16-bit timer capture/ compare register 000 (μPD78F9 20x only) Cautions Page The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed. pp. 93, 125 The capture operation may not be performed for CR000 set in compare mode even if a capture trigger is input. pp.
APPENDIX D LIST OF CAUTIONS Soft Classification 16-bit timer/ event counters 00 (μPD78F 920x only) Details of Function TMC00: 16-bit timer mode control register 00 Cautions Hard Soft Soft Hard Soft TOC00: 16-bit timer output control register 00 Page Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is disabled. pp.
APPENDIX D LIST OF CAUTIONS Hard Classification Soft Chapter 6 Chapter (5/15) Function Details of Function Cautions 16-bit timer/ event counters 00 PRM00: The sampling clock used to eliminate noise differs when a TI000 valid edge is Prescaler mode used as the count clock and when it is used as a capture trigger. In the former register 00 case, the count clock is fXP, and in the latter case the count clock is selected by prescaler mode register 00 (PRM00).
APPENDIX D LIST OF CAUTIONS Hard Classification Soft Chapter 6 Chapter (6/15) Function 16-bit timer/ event counters 00 Details of Function Cautions Timer start errors An error of up to one clock may occur in the time required for a match signal to be p. 124 generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
APPENDIX D LIST OF CAUTIONS Soft Classification Details of Function 8-bit timer PWM output H1 Cautions Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are within the following range. Page p. 141 00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH Soft Chapter 8 Chapter 7 Chapter (7/15) Function Watchdog WDTM: Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values.
APPENDIX D LIST OF CAUTIONS Soft Classification Hard Soft Chapter 9 Chapter (8/15) Function Details of Function Cautions A/D converter ADM: A/D If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped converter mode (ADCS = 0) and then A/D conversion is started, execute two NOP instructions or an instruction equivalent to two machine cycles, and set ADCS to 1. (μPD78F9 register 20x only) A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2. Page p.
APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 9 Chapter (9/15) Function A/D converter Details of Function Cautions Noise To maintain the 10-bit resolution, attention must be paid to noise input to the VDD countermeasures pin and ANI0 to ANI3 pins. (μPD78F9 20x only) Page p. 173 <1> Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply.
APPENDIX D LIST OF CAUTIONS A/D converter (μPD78F9 20x only) Soft Chapter Chapter 10 Hard Chapter 9 Soft Classification (10/15) Function Interrupt functions Details of Function Cautions A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to the A/D converter mode register (ADM) p. 175 and analog input channel specification register (ADS), the contents of ADCR and ADCRH may become undefined.
APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 11 Chapter (11/15) Function Standby function Details of Function HALT mode setting and operating Hard Reset function Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag clear, the standby mode is immediately cleared if set. p.
APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 14 Chapter (12/15) Function Lowvoltage detector Details of Function Cautions for low-voltage detector Cautions In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. Page p. 215 <1> When used as reset The system may be repeatedly reset and released from the reset status.
APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 15 Chapter (13/15) Function Option byte Details of Function Low-speed internal oscillates Cautions Page If it is selected that low-speed internal oscillator can be stopped by software, pp. 221, supply of the count clock to WDT is stopped in the HALT/STOP mode, regardless 223 of the setting of bit 0 (LSRSTOP) of the low-speed internal oscillation mode register (LSRCM).
APPENDIX D LIST OF CAUTIONS Chapter Chapter 16 Soft Classification (14/15) Function Flash memory Details of Function Self programming function Cautions Page The state of the pins in self programming mode is the same as that in HALT mode. p. 237 Since the security function set via on-board/off-board programming is disabled in self programming mode, the self programming command can be executed regardless of the security function setting.
APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 17 Chapter (15/15) Function On-chip debug function Details of Function Connecting QB-MINI2 to 78K0S/KU1+ Cautions The 78K0S/KU1+ has an on-chip debug function, which is provided for development and evaluation.
APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition Page Description Throughout Addition of μPD78F950x products (without 16-bit timer/event counter and A/D converter ) p. 6 Modification of Related Documents p. 17 Modification of 1.4 78K0S/Kx1+ Product Lineup p. 226 16.4 Writing with Flash Memory Programmer • Deletion of FlashPro4 and addition of QB-MINI2 • Modification of Remark p.
APPENDIX E REVISION HISTORY E.2 Revision History up to Previous Editions The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/2) Edition 2nd edition Description Applied to: Modification of 1.1 Features CHAPTER 1 Addition of Note 2 to 5 in 1.4 78K0S/Kx1+ Product Lineup OVERVIEW 9.
APPENDIX E REVISION HISTORY (2/2) Edition 2nd edition Description Applied to: APPENDIX B NOTES Addition of this chapter ON DESIGNING TARGET SYSTEM User’s Manual U18172EJ3V0UD 339
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