Datasheet

78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0010EJ0500 Rev.5.00 707
Feb 28, 2012
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
28.5.2 Internal voltage (1.2 V) generator for analog input of A/D converter
(T
A = 40 to +105C, 2.7 V  AVREF  VDD  5.5 V, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output voltage range VOFO 1.14 1.18 1.22 V
Operation stabilization wait time
Note
tFO 10  s
Note This is the time from enabling the operation to generate the internal voltage (1.2 V) (V12SEL bit = 1) until an A/D
conversion operation can be performed.
28.5.3 PGA
(T
A = 40 to +105C, 2.7 V  AVREF  VDD  5.5 V, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input offset voltage VIOPGA 5 10 mV
Input voltage range VIPGA 0.1AVREF/
gain
0.9AVREF/
gain
V
Maximum output voltage VOPGA 0.1AVREF 0.9AVREF V
4, 8 times
1 %
16 times
1.5 %
Gain error
32 times
2 %
4, 8 times
4 V/
 s
4.0 V  AVREF
 5.5 V
16, 32 times
1.5 V/
 s
4, 8 times
1.8 V/
 s
SRRPGA Rising
edge
2.7 V  AV
REF
< 4.0 V
16, 32 times
0.5 V/
 s
4, 8 times
3.2 V/
 s4.0 V  AVREF
 5.5 V
16, 32 times
1.5 V/
 s
4, 8 times
1.2 V/
 s
Slew rate
SR
FPGA Falling
edge
2.7 V  AV
REF
< 4.0 V
16, 32 times
0.5 V/
 s
4, 8 times
5
 s Operation stabilization wait time
Note
tPGA
16, 32 times
10
 s
Note Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after the PGA
operation has been enabled (PGAEN = 1).