Datasheet
78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE
R01UH0010EJ0500 Rev.5.00 81
Feb 28, 2012
Table 3-9. Special Function Register List : 78K0/IB2 (32 Pins) (4/7)
Bit No. Number of Bits
Manipulated
Simultaneously
Address Symbol
7 6 5 4 3 2 1 0
R/W
1 8 16
After
Reset
Reference
page
FF6AH
FF6BH
FF6CH TMHMD1
<TMHE
1>
CKS12 CKS11 CKS10
TMMD
11
TMMD
10
<TOLE
V1>
<TOEN
1>
R/W 00H 341
FF6DH TMCYC1 0 0 0 0 0 RMC1 NRZB1
<NRZ1>
R/W 00H 343
FF6EH HIZTREN
<HIZT
REN0>
0 0 0 0 0 0 0 R/W 00H 250
FF6FH HIZTRS
<HIZT
RS1>
<HIZT
RS0>
0 0
<HIZP
TS3>
<HIZP
TS2>
<HIZP
TS1>
<HIZP
TS0>
R/W 00H 251
FF70H
MULAL
R/W 00H 574
FF71H
MU
LA
MULAH
R/W
00H 574
FF72H
MULBL
R/W 00H 574
FF73H
MU
LB
MULBH
R/W
00H 574
FF74H
FF75H
MUL0H
R 0000H 573
FF76H
FF77H
MUL0L
R 0000H 573
FF78H HZA0CTL0
<HZA0
DCE0>
<HZA0
DCM0>
<HZA0
DCN0>
<HZA0
DCP0>
<HZA0
DCT0>
<HZA0
DCC0>
0
<HZA0
DCF0>
R/W 00H 252
FF79H to
FF7BH
FF7CH SOTB11 R/W 00H 555
FF7DH
FF7EH TX0CTL0
<TX0
TMC>
0 0 0 0
<TX0
CKS2>
<TX0
CKS1>
<TX0
CKS0>
R/W 00H 206
FF7FH TX0CTL1
<TX0IN
TPST>
0
<TX0PW
MCE>
<TX0PW
MCINV>
<TX0P
WM>
0 0 0 R/W 00H 208
FF80H TX0CTL2 0
<TX0T
RGS>
0 0 0 0
<TX0A
DEN>
<TX0C
CS>
R/W 00H 209
FF81H TX0CTL3 0
<TX0C
MPLD
SET1>
<TX0C
MPLD
SET0>
0
<TX0IN
TP0RM
1>
<TX0IN
TP0RM
0>
<TX0C
MP2R
M1>
<TX0C
MP2R
M0>
R/W 00H 211
FF82H TX0CTL4 0 0
<TX0CM
P1RP>
<TX0CM
P1RM1>
<TX0CM
P1RM0>
<TX0CM
P0RP>
<TX0CM
P0RM1>
<TX0CM
P0RM0>
R/W 00H 213
FF83H TX0IOC0 0 0 0 0
<TX0T
OC1>
<TX0T
OC0>
<TX0T
OL1>
<TX0T
OL0>
R/W 00H 215
FF84H
FF85H
TX0CR0
R/W 0000H 204
FF86H
FF87H
TX0CR1
R/W 0000H 204
Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0, and is
defined as an sfr variable using the #pragma sfr directive in the CC78K0.