Datasheet

78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE
R01UH0010EJ0500 Rev.5.00 75
Feb 28, 2012
Table 3-8. Special Function Register List : 78K0/IB2 (30 Pins) (5/7)
Bit No. Number of Bits
Manipulated
Simultaneously
Address Symbol
7 6 5 4 3 2 1 0
R/W
1 8 16
After
Reset
Reference
page
FF88H CSIM11
<CSIE
11>
TRMD
11
SSE11 DIR11 0 0 0
CSOT1
1
R/W 00H 556
FF89H CSIC11 0 0 0 CKP11 DAP11
CKS11
2
CKS11
1
CKS11
0
R/W 00H 557
FF8AH
FF8BH
TX0CR2
R/W 0000H 204
FF8CH TCL51 0 0 0 0 0
TCL51
2
TCL51
1
TCL51
0
R/W 00H 331
FF8DH to
FF8FH
FF90H
FF91H
TX0CR3
R/W 0000H 204
FF92H
FF93H
TX0CCR0
R/W 0000H 204
FF94H TX1CTL0
<TX1T
MC>
0 0 0 0
<TX1C
KS2>
<TX1C
KS1>
<TX1S
KS0>
R/W 00H 206
FF95H TX1CTL1 0 0
<TX1PW
MCE>
0
<TX1P
WM>
0
<TX1M
D1>
<TX1M
D0>
R/W 00H 208
FF96H TX1CTL2 0 0 0 0 0 0
<TX1A
DEN>
<TX1C
CS>
R/W 00H 209
FF97H
FF98H
FF99H WDTE R/W
1AH/
9AH
Note1
364
FF9AH TX1CTL4 0 0 0
<TX1C
MP1R
M1>
<TX1C
MP1R
M0>
0
<TX1C
MP0R
M1>
<TX1C
MP0R
M0>
R/W 00H 213
FF9BH TX1IOC0 0 0 0 0
<TX1T
OC1>
<TX1T
OC0>
<TX1T
OL1>
<TX1T
OL0>
R/W 00H 215
FF9CH
FF9DH
TX1CR0
R/W 0000H 204
FF9EH
FF9FH OSCCTL
<EXCL
K>
<OSCS
EL>
0 0 0 0 0 0 R/W 00H 172
FFA0H RCM
<RSTS>
0
<PLLS>
<PLLO
N>
<SELP
LL>
0
<LSR
STOP>
<RSTO
P>
R/W
80H
Note2
174
Notes 1. The reset value of WDTE is determined by setting of option byte.
2. The value of this register is 00H immediately after a reset release but automatically changes to 80H after oscillation
accuracy stabilization of high-speed internal oscillator has been waited.
Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0, and is
defined as an sfr variable using the #pragma sfr directive in the CC78K0.