Datasheet

78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE
R01UH0010EJ0500 Rev.5.00 72
Feb 28, 2012
Table 3-8. Special Function Register List : 78K0/IB2 (30 Pins) (2/7)
Bit No. Number of Bits
Manipulated
Simultaneously
Address Symbol
7 6 5 4 3 2 1 0
R/W
1 8 16
After
Reset
Reference
page
FF24H
FF25H
FF26H PM6 1 1 1 1 1 1 PM61 PM60 R/W FFH 148
FF27H PM7 1 1 1 1 1 1 1 PM70 R/W FFH 148
FF28H ADM0
<ADCS>
0 FR2 FR1 FR0 LV1 LV0
<ADCE>
R/W 00H 373
FF29H
FF2AH POM6 0 0 0 0 0 0
POM6
1
POM6
0
R/W 00H
155, 449,
496
FF2BH
FPCTL 0 0 0 0 0 0 0
<FLMD
PUP>
R/W 00H 670
FF2CH
FF2DH RSTMASK 0 0 RSTM 0 0 0 0 0 R/W 00H 155
FF2EH ADPC0
ADPC
S7
ADPC
S6
ADPC
S5
ADPC
S4
ADPC
S3
ADPC
S2
ADPC
S1
ADPC
S0
R/W 00H
155, 382,
408, 425
FF2FH ADPC1 0 0 0 0 0 0 0
ADPC
S8
R/W 00H 155, 382
FF30H PU0 0 0 0 0 0 PU02 PU01 PU00 R/W 00H 152
FF31H
FF32H
FF33H PU3 PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30 R/W 00H 152
FF34H
FF35H
FF36H PU6 0 0 0 0 0 0 PU61 PU60 R/W 00H 152
FF37H
FF38H
FF39H MUXSEL 0
<INTP0
SEL0>
0
<TM00
SEL0>
0 0 0 0 R/W 00H
157, 270,
332, 344,
592
FF3AH
FF3BH
FF3CH PU12 0 0 PU125 0 0 0 0 0 R/W 20H 152
FF3DH RMC R/W 00H 649
FF3EH PIM6 0 0 0 0 0 0 PIM61 PIM60 R/W 00H
154, 495
FF3FH
FF40H
FF41H CR51 R/W 00H 330
FF42H
FF43H TMC51
<TCE51>
0
0 0 0 0 0
0 R/W 00H 332
FF44H to
FF47H
Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0, and
is defined as an sfr variable using the #pragma sfr directive in the CC78K0.