Datasheet
78K0/Ix2 APPENDIX C REVISION HISTORY
R01UH0010EJ0500 Rev.5.00 741
Feb 28, 2012
(6/7)
Edition Description Chapter
Deletion of Caution of (2) Control mode in 2.2.4 P60 and P61 (port 6)
Addition of Note 3 to Table 2-2. Pin I/O Circuit Types (78K0/IY2) to Table 2-4. Pin I/O
Circuit Types (78K0/IB2 (30 Pins))
Change of Table 2-3. Pin I/O Circuit Types (78K0/IA2) and Table 2-4. Pin I/O Circuit
Types (78K0/IB2 (30 Pins))
CHAPTER 2 PIN
FUNCTIONS
Change of FLMDPUP bit to a reserved word in Table 3-6. Special Function Register
List to Table 3-8. Special Function Register List
CHAPTER 3 CPU
ARCHITECTURE
Change of (1) 78K0/IA2, 78K0/IB2 (32 Pins) of Figure 4-1. Block Diagram of P00
Change of (2) 78K0/IA2, 78K0/IB2 of Figure 4-5. Block Diagram of P21
Change of (1) 78K0/IY2, 78K0/IA2, 78K0/IB2 (32 Pins) of Figure 4-16 Block Diagram
of P34
CHAPTER 4 PORT
FUNCTIONS
Change of Figure 6-3. Block Diagram of 16-Bit Timers X0 and X1
Change of 6.4 Operation of 16-Bit Timers X0 and X1
Change of Figure 6-38. Timing of Interlocking mode 1 (timer reset mode) and Figure
6-40. Timing of Interlocking mode 2 (timer restart mode)
Change of Figure 6-42. Timing of Interlocking mode 3 (timer output reset mode)
Addition of (4) Priority when multiple interlocking modes occur to 6.5 Interlocking
Function with Comparator or INTP0
CHAPTER 6 16-BIT
TIMERS X0 AND X1
Change of Figure 11-1. Block Diagram of A/D Converter
CHAPTER 11 A/D
CONVERTER
Change of Note of Figure 13-11. Example of Setting Procedure when Starting
Comparator Operation (Using Internal Reference Voltage for Comparator Reference
Voltage)
CHAPTER 13
COMPARATORS
Change of Table 19-3. Operating Statuses in STOP Mode
CHAPTER 19
STANDBY FUNCTION
Change of Note 2 of Table 20-2. Hardware Statuses After Reset Acknowledgment
(4/4)
Change of Table 20-3. RESF Status When Reset Request Is Generated
CHAPTER 20 RESET
FUNCTION
Change of Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-
Clear Circuit and Low-Voltage Detector (2/2)
CHAPTER 21 POWER-
ON-CLEAR CIRCUIT
Change of Note 1 of Figure 22-2. Format of Low-Voltage Detection Register (LVIM)
Change of Figure 22-3. Format of Low-Voltage Detection Level Select Register
(LVIS)
Change of Remark of (1) Used as reset (LVIMD = 1) in 22.4 Operation of Low-Voltage
Detector
Change of (2) When LVI default start function enabled is set (LVISTART = 1) of 22.4.1 When
used as reset
Change of Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(LVISTART = 1)
Change of (2) When LVI default start function enabled is set (LVISTART = 1) of
22.4.2 When used as interrupt
Change of Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation
(LVISTART = 1)
CHAPTER 22 LOW-
VOLTAGE DETECTOR
Deletion of "(To be prepared)" and change of document no. of related documents CHAPTER 23
REGULATOR
Change of Figure 24-1. Format of Option Byte (2/3) CHAPTER 24 OPTION
BYTE
Deletion of "(To be prepared)" and change of document no. of related documents
4th Edition
Change of document no. of related documents
CHAPTER 25 FLASH
MEMORY