Datasheet

78K0/Ix2 APPENDIX C REVISION HISTORY
R01UH0010EJ0500 Rev.5.00 739
Feb 28, 2012
(4/7)
Edition Description Chapter
Addition of Note to Figure 13-13 Example of Setting Procedure when Starting
Comparator Operation (Using Input Voltage from Comparator Common (CMPCOM)
Pin for Comparator Reference Voltage (78K0/IB2 only))
Modification of Figure 13-14 Example of Setting Procedure when Stopping
Comparator Operation
CHAPTER 13
COMPARATORS
Addition of the port output mode register 6 (POM6) to Table 14-1 Configuration of
Serial Interface UART6/DALI
Addition of Note 2 to Figure 14-4 Block Diagram of Serial Interface UART6/DALI
Modification of Caution in 14.2 (1) UART receive buffer register 6 (RXB6) and (2)
DALI receive buffer register (RXBDL)
Addition of (10) Port output mode register 6 (POM6) to 14.3 Registers Controlling
Serial Interface UART6/DALI
Addition of the port output mode register 6 (POM6) to 14.4.2 (1) Registers used
Modification of Table 14-2 Relationship Between Register Settings and Pins
Addition of the port output mode register 6 (POM6) to 14.4.3 (3) Registers used
Modification of Table 14-4 Relationship Between Register Settings and Pins
CHAPTER 14 SERIAL
INTERFACE
UART6/DALI
Modification of Figure 15-1 Block Diagram of Serial Interface IICA
Addition of Caution 3 to Figure 15-3 Format of IICA Shift Register (IICA)
Addition of Note 3 to, and modification of Caution in Figure 15-5 Format of IICA
Control Register 0 (IICACTL0) (1/4)
Addition of description of the SPIE0 bit to Figure 15-5 Format of IICA Control Register
0 (IICACTL0) (2/4)
Modification of description of the STT0 bit in Figure 15-5 Format of IICA Control
Register 0 (IICACTL0) (3/4)
Modification of Caution in Figure 15-5 Format of IICA Control Register 0 (IICACTL0)
(4/4)
Modification of Figure 15-6 Format of IICA Status Register 0 (IICAS0) (2/3)
Partial deletion of description in 15.3 (9) Port mode register 6 (PM6)
Modification of 15.4.2 Setting transfer clock by using IICWL and IICWH registers
CHAPTER 15 SERIAL
INTERFACE IICA
Addition of Caution 2 to 19.1.1 Standby function
Modification of Figure 19-4 HALT Mode Release by Reset
Addition of Caution 2 to Table 19-3. Operating Statuses in STOP Mode
Addition of Note 1 to Figure 19-5 Operation Timing When STOP Mode Is Released
(When Unmasked Interrupt Request Is Generated)
Addition of Note 2 to (3) When internal high-speed oscillation clock is used as CPU
clock in Figure 19-6 STOP Mode Release by Interrupt Request Generation
Modification of Figure 19-7 STOP Mode Release by Reset
CHAPTER 19
STANDBY FUNCTION
Modification of Figure 20-1 Block Diagram of Reset Function to Figure 20-4 Timing
of Reset in STOP Mode by RESET Input
CHAPTER 20 RESET
FUNCTION
Modification of Figure 21-2 Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector
CHAPTER 21 POWER-
ON-CLEAR CIRCUIT
Modification of Figure 22-3 Format of Low-Voltage Detection Level Select Register
(LVIS)
CHAPTER 22 LOW-
VOLTAGE DETECTOR
Modification of 23.1 Regulator Overview
Modification and addition of Caution 4 to Figure 23-1. Format of Regulator Mode
Control Register (RMC)
Deletion of Table 23-1. Regulator Output Voltage Conditions
3rd Edition
Addition of 23.3 Cautions for Self Programming
CHAPTER 23
REGULATOR