Datasheet

78K0/Ix2 APPENDIX C REVISION HISTORY
R01UH0010EJ0500 Rev.5.00 738
Feb 28, 2012
(3/7)
Edition Description Chapter
Modification of 6.4 (1) PWM output operation (single output) to (4) PWM output
operation (TMX0 and TMX1 synchronous start mode)
Addition of Notes 1, 2 to Figure 6-34 Block Diagram of 16-Bit Timer X0 Output
Configuration to Figure 6-36. Block Diagram of 16-Bit Timers X0 and X1 Output
Configuration
Modification of 6.5 (1) Interlocking mode 1 (timer reset mode) to (3) Interlocking
mode 3 (timer output reset mode)
Modification of Figure 6-46 Format of High-impedance Output Function Control
Register 0 (HZA0CTL0) (2/2)
CHAPTER 6 16-BIT
TIMERS X0 AND X1
Modification of Figure 8-1 Block Diagram of 8-Bit Timer/Event Counter 51 CHAPTER 8 8-BIT
TIMER/EVENT
COUNTER 51
Modification of Figure 11-1 Block Diagram of A/D Converter
Modification of mode representation in Figure 11-3. Timing Chart When Comparator
Is Used
Modification of mode representation in Table 11-2. A/D Conversion Time Selection
Modification of Figure 11-10 Format of Analog Input Channel Specification Register
(ADS) (2/2) and Caution 3
Modification of Table 11-3 Setting Functions of P20/ANI0/AMP-, P22/ANI2/AMP+
Pins to Table 11-6 Setting Functions of P26/ANI6/CMPCOM Pin
Modification of Cautions 2, 4 in 11.4.1 Basic operation of A/D converter (software
trigger mode) and 11.4.2 Basic operations of A/D converter (timer trigger mode) in
old edition
Modification of Caution 2 in 11.4.4 A/D converter trigger mode selection
Modification of Cautions 2, 6 of Software trigger mode in 11.4.5 A/D converter
operation mode
Modification of Cautions 2, 6 of Timer trigger mode in 11.4.5 A/D converter operation
mode
Modification of Table 11-9 Resistance and Capacitance Values of Equivalent Circuit
(Reference Values)
CHAPTER 11 A/D
CONVERTER
Addition of the analog input channel specification register (ADS) to Table 12-1
Configuration of Operational Amplifier
Modification of Figure 12-1 Block Diagram of Operational Amplifier
Addition of the analog input channel specification register (ADS) to 12.3 Registers Used
in Operational Amplifier
Modification of Caution 3 in Figure 12-2. Format of Operational Amplifier 0 Control
Register (AMP0M) (Products with Operational Amplifier Only)
Modification of Table 12-2 Setting Functions of P20/ANI0/AMP-, P22/ANI2/AMP+
Pins and Table 12-3 Setting Functions of P21/ANI1/AMPOUT/PGAIN Pin
CHAPTER 12
OPERATIONAL
AMPLIFIERS
Modification of 13.1 Features of Comparators
Modification of Figure 13-1 Block Diagram of Comparators
Modification of Figure 13-2 Format of Comparator 0 Control Register (C0CTL) to
Figure 13-4 Format of Comparator 2 Control Register (C2CTL)
Modification of Figure 13-5 Format of DA0 Internal Reference Voltage Selection
Register (C0RVM) to Figure 13-7 Format of DA2 Internal Reference Voltage
Selection Register (C2RVM)
Modification of Table 13-2. Setting Functions of P23/ANI3/CMP2+, P24/ANI4/CMP0+,
P25/ANI5/CMP1+ Pins and Table 13-3. Setting Functions of P26/ANI6/CMPCOM Pin
3rd Edition
Modification of Note in Figure 13-11 Example of Setting Procedure when Starting
Comparator Operation (Using Internal Reference Voltage for Comparator
Reference Voltage)
CHAPTER 13
COMPARATORS