Datasheet

78K0/Ix2 APPENDIX C REVISION HISTORY
R01UH0010EJ0500 Rev.5.00 737
Feb 28, 2012
(2/7)
Edition Description Chapter
Modification of Related Documents INTRODUCTION
Modification of description in 1.1 Features
Modification of [Port Number] and [Example of Port Number] in 1.2 Ordering
Information
Modification of description in 1.5 Outline of Functions
CHAPTER 1 OUTLINE
Modification of description of RESET pin
Addition of Caution 2 to 2.2.5 P70 (port 7)
Addition of Caution to 2.2.6 P121, P122, and P125 (port 12)
Modification of, and deletion of Note 3 in Table 2-2. Pin I/O Circuit Types (78K0/IY2)
Modification of, and deletion of Note 3 in Table 2-3. Pin I/O Circuit Types (78K0/IA2)
Modification and deletion of Note 3 in Table 2-4. Pin I/O Circuit Types (78K0/IB2)
Modification of Type 42 to Type 42-A in Figure 2-1. Pin I/O Circuit List (3/3)
CHAPTER 2 PIN
FUNCTIONS
Modification of Table 3-6 Special Function Register List: 78K0/IY2 to Table 3-8
Special Function Register List: 78K0/IA2
CHAPTER 3 CPU
ARCHITECTURE
Modification of Table 4-6 Setting Functions of P20/ANI0/AMP-, P22/ANI2/AMP+ Pins
to Table 4-9 Setting Functions of P26/ANI6/CMPCOM Pin
Addition of Caution 3 to 4.2.6 Port 12
Modification of Figure 4-23 Block Diagram of P121, P122
Addition of Caution to Figure 4-24. Block Diagram of P125
Addition of description to 4.3 (5) Port output mode register 6 (POM6)
Addition of Note 3 to Table 4-13 Settings of Port Mode Register and Output Latch
When Using Alternate Function (78K0/IA2) (2/2)
Addition of Note 3 to Table 4-14 Settings of Port Mode Register and Output Latch
When Using Alternate Function (78K0/IB2) (2/2)
CHAPTER 4 PORT
FUNCTIONS
Addition of Note to Figure 5-1 Block Diagram of Clock Generator
Addition of Caution 1 to Figure 5-5 Format of Main OSC Control Register (MOC)
Modification of Figure 5-12 Clock Generator Operation When Power Supply Voltage
Is Turned On, (When LVI Default Start Function Stopped Is Set (Option Byte:
LVISTART = 0)) and Figure 5-13 Clock Generator Operation When Power Supply
Voltage Is Turned On (When LVI Default Start Function Enabled Is Set (Option
Byte: LVISTART = 1))
Modification of Figure 5-14. CPU Clock Status Transition Diagram (When LVI Default
Start Mode Function Stopped Is Set (Option Byte: LVISTART = 0))
Addition of Caution to Table 5-4. CPU Clock Transition and SFR Register Setting
Examples (3/3)
CHAPTER 5 CLOCK
GENERATOR
Addition of (6) Timer output gating function (by interlocking with 8-bit timer H1) to
(10) High-impedance output control function (by interlocking with comparator and
INTP0) to 6.1 Functions of 16-Bit Timers X0 and X1
Modification of Figure 6-2 Block Diagram of 16-Bit Timer X1
Addition of Caution to 6.2 (1) 16-bit timer Xn capture/compare register 0 (TXnCCR0)
Modification of, and addition of Caution 3 to Figure 6-8 Format of 16-Bit Timer X0
Operation Control Register 1 (TX0CTL1)
Addition of Caution 3 to Figure 6-9 Format of 16-Bit Timer X1 Operation Control
Register 1 (TX1CTL1)
Addition of Cautions 2, 3 to Figure 6-10 Format of 16-Bit Timer X0 Operation Control
Register 2 (TX0CTL2) and Figure 6-11 Format of 16-Bit Timer X1 Operation Control
Register 2 (TX1CTL2)
3rd Edition
Modification of Figure 6-12 Format of 16-Bit Timer X0 Operation Control Register 3
(TX0CTL3) to Figure 6-14 Format of 16-Bit Timer X1 Operation Control Register 4
(TX1CTL4)
CHAPTER 6 16-BIT
TIMERS X0 AND X1