Datasheet
78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE
R01UH0010EJ0500 Rev.5.00 62
Feb 28, 2012
Table 3-6. Special Function Register List : 78K0/IY2 (5/6)
Bit No.
Number of Bits
Manipulated
Simultaneously
Address Symbol
7 6 5 4 3 2 1 0
R/W
1 8 16
After
Reset
Reference
page
FF9AH TX1CTL4 0 0 0
<TX1C
MP1R
M1>
<TX1C
MP1R
M0>
0
<TX1C
MP0R
M1>
<TX1C
MP0R
M0>
R/W 00H 213
FF9BH TX1IOC0 0 0 0 0
<TX1T
OC1>
<TX1T
OC0>
<TX1T
OL1>
<TX1T
OL0>
R/W 00H 215
FF9CH
FF9DH
TX1CR0
R/W 0000H 204
FF9EH
FF9FH OSCCTL
<EXCL
K>
<OSCS
EL>
0 0 0 0 0 0 R/W 00H 172
FFA0H RCM
<RSTS>
0
<PLLS>
<PLLO
N>
<SELP
LL>
0
<LSR
STOP>
<RSTO
P>
R/W
80H
Note1
174
FFA1H MCM 0 0 0 0 0
<XSEL>
<MCS>
<MCM
0>
R/W 00H 177
FFA2H MOC
<MST
OP>
0 0 0 0 0 0 0 R/W 80H 176
FFA3H OSTC 0 0 0
MOST1
1
MOST1
3
MOST
14
MOST
15
MOST1
6
R 00H 178, 606
FFA4H OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 R/W 05H 179, 607
FFA5H
to FFABH
FFACH RESF 0 0 0
WDTRF
0 0 0 LVIRF R
00H
Note2
628
FFADH to
FFAFH
FFB0H
FFB1H
TX1CR1
R/W 0000H 204
FFB2H
FFB3H
TX1CR2
R/W 0000H 204
FFB4H
FFB5H
TX1CR3
R/W 0000H 204
FFB6H
FFB7H
TX1CCR0
R/W 0000H 204
FFB8H
FFB9H
FFBAH TMC00 0 0 0 0
TMC003 TMC002
0
<OVF0
0>
R/W 00H 263
FFBBH PRM00 0 0 ES010 ES000 0 0
PRM001 PRM000
R/W 00H 268
FFBCH CRC00 0 0 0 0 0
CRC002 CRC001 CRC000
R/W 00H 264
Notes 1. The value of this register is 00H immediately after a reset release but automatically changes to 80H after oscillation
accuracy stabilization of high-speed internal oscillator has been waited.
2. The reset value of RESF varies depending on the reset source.
Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0, and is
defined as an sfr variable using the #pragma sfr directive in the CC78K0.