Datasheet
78K0/Ix2 CHAPTER 31 CAUTIONS FOR WAIT
R01UH0010EJ0500 Rev.5.00 724
Feb 28, 2012
Table 31-1. Registers That Generate Wait and Number of CPU Wait Clocks (2/2)
Peripheral
Hardware
Register Access Number of Wait Clocks
Serial interface
UART6/DALI
ASIS6 Read 1 clock (fixed)
Serial interface
IICA
IICAS0 Read 1 clock (fixed)
ADM0 Write
ADS Write
ADPC0, ADPC1 Write
ADCR, ADCRH, ADCRL,
ADCRX0, ADCRX1,
ADCRX0L, ADCRX1L
Read
1 to 5 clocks (when f
AD = fPRS/2 is selected)
1 to 7 clocks (when f
AD = fPRS/3 is selected)
1 to 9 clocks (when f
AD = fPRS/4 is selected)
2 to 13 clocks (when f
AD = fPRS/6 is selected)
2 to 17 clocks (when f
AD = fPRS/8 is selected)
2 to 25 clocks (when f
AD = fPRS/12 is selected)
A/D converter
The above number of clocks is when the same source clock is selected for CPU and peripheral hardware.
The number of wait clocks can be calculated by the following expression and under the following conditions.
<Calculating number of wait clocks>
Number of wait clocks =
2 f
CPU
f
AD
+ 1
* Fraction is truncated if the number of wait clocks 0.5 and rounded up if the number of wait clocks > 0.5.
<Conditions for maximum/minimum number of wait clocks>
Maximum number of times: Maximum speed of CPU (f
XP), lowest speed of A/D conversion clock (fPRS/12)
Minimum number of times: Minimum speed of CPU (f
XP/16), highest speed of A/D conversion clock (fPRS)
f
AD: A/D conversion clock frequency (fPRS to fPRS/12)
f
CPU: CPU clock frequency
f
PRS: Peripheral hardware clock frequency
f
XP: Main system clock frequency
Caution When the peripheral hardware clock (f
PRS) is stopped, do not access the registers listed above using an
access method in which a wait request is issued.
Remark The clock is the CPU clock (f
CPU).