Datasheet

78K0/Ix2 CHAPTER 31 CAUTIONS FOR WAIT
R01UH0010EJ0500 Rev.5.00 723
Feb 28, 2012
CHAPTER 31 CAUTIONS FOR WAIT
31.1 Cautions for Wait
This product has two internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.
Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may
be passed if an access to the CPU conflicts with an access to the peripheral hardware.
When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes processing,
until the correct data is passed.
As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of execution
clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, refer to Table 31-1). This
must be noted when real-time processing is performed.
31.2 Peripheral Hardware That Generates Wait
Table 31-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks.
Table 31-1. Registers That Generate Wait and Number of CPU Wait Clocks (1/2)
Peripheral
Hardware
Register Access Number of Wait Clocks
TX0CCR0, TX1CCR0
(during capture operation)
Read 3 clocks
16-bit timers
X0, X1
The above number of clocks is when the same source clock is selected for CPU and 16-bit timers X0 and
X1. The number of wait clocks can be calculated by the following expression and under the following
conditions.
<Calculating number of wait clocks>
 Number of wait clocks =
3 f
CPU
f
TMXS
+ 1
* Fraction is truncated if the number of wait clocks/f
CPU  the low-level width of CPU clock and rounded up
if the number of wait clocks/f
CPU > the low-level width of CPU clock.
<Conditions for maximum/minimum number of wait clocks>
 Maximum number of times: Maximum speed of CPU (20 MHz), lowest speed of TMX0 and TMX1 clock
(156.25 kHz)
 Minimum number of times: Minimum speed of CPU (1.25 MHz), highest speed of TMX0 and TMX1 clock
(40 MHz: when f
TMX is used/20 MHz: when fPRS is used)
f
TMXS: 16-bit timers X0 and X1 selection clock frequency
f
TMX: TMX control clock frequency
f
CPU: CPU clock frequency
f
PRS: Peripheral hardware clock frequency
Caution When the peripheral hardware clock (f
PRS) is stopped, do not access the registers listed above using an
access method in which a wait request is issued.
Remark The clock is the CPU clock (f
CPU).