Datasheet
78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE
R01UH0010EJ0500 Rev.5.00 60
Feb 28, 2012
Table 3-6. Special Function Register List : 78K0/IY2 (3/6)
Bit No.
Number of Bits
Manipulated
Simultaneously
Address Symbol
7 6 5 4 3 2 1 0
R/W
1 8 16
After
Reset
Reference
page
FF60H
AMP0M
Note
0
<PGAE
N>
0 0 0 0
<AMP0
VG1>
<AMP0
VG0>
R/W 00H 407
FF61H
FF62H C0CTL
<CMP0
EN>
<C0DF
S1>
<C0DF
S0>
<C0MO
DSEL1>
<C0MO
DSEL0>
0 <C0OE>
<C0IN
V>
R/W
00H 416
FF63H C0RVM
<CVRE>
0 0
<C0VR
S4>
<C0VR
S3>
<C0VR
S2>
<C0VR
S1>
<C0VR
S0>
R/W
00H 420
FF64H C1CTL
<CMP1
EN>
<C1DF
S1>
<C1DF
S0>
<C1MO
DSEL1>
<C1MO
DSEL0>
0
<C1OE>
<C1IN
V>
R/W
00H 416
FF65H C1RVM 0 0 0
<C1VR
S4>
<C1VR
S3>
<C1VR
S2>
<C1VR
S1>
<C1VR
S0>
R/W
00H 420
FF66H C2CTL
<CMP2
EN>
<C2DF
S1>
<C2DF
S0>
<C2MO
DSEL1>
<C2MO
DSEL0>
0
<C2OE>
<C2IN
V>
R/W
00H 416
FF67H C2RVM 0 0 0
<C2VR
S4>
<C2VR
S3>
<C2VR
S2>
<C2VR
S1>
<C2VR
S0>
R/W
00H 420
FF68H
FF69H CMPFLG 0 0 0 0 0
<CMP2
F>
<CMP1
F>
<CMP0
F>
R
00H 424
FF6AH
FF6BH
FF6CH TMHMD1
<TMHE
1>
CKS12 CKS11 CKS10
TMMD
11
TMMD
10
<TOLE
V1>
<TOEN
1>
R/W
00H 341
FF6DH TMCYC1 0 0 0 0 0 RMC1 NRZB1
<NRZ1>
R/W
00H 343
FF6EH HIZTREN
<HIZTR
EN0>
0 0 0 0 0 0 0 R/W
00H 250
FF6FH HIZTRS
<HIZTR
S1>
<HIZTR
S0>
0 0
<HIZPT
S3>
<HIZPT
S2>
<HIZPT
S1>
<HIZPT
S0>
R/W
00H 251
FF70H MULAL
R/W
00H
574
FF71H
MU
LA
MULAH
R/W
00H
574
FF72H MULBL
R/W
00H
574
FF73H
MU
LB
MULBH
R/W
00H
574
FF74H
FF75H
MUL0H
R
0000H
573
FF76H
FF77H
MUL0L
R
0000H
573
FF78H HZA0CTL0
<HZA0
DCE0>
<HZA0
DCM0>
<HZA0
DCN0>
<HZA0
DCP0>
<HZA0
DCT0>
<HZA0
DCC0>
0
<HZA0
DCF0>
R/W 00H 252
Note This register is incorporated only in products with operational amplifier.
Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0, and is
defined as an sfr variable using the #pragma sfr directive in the CC78K0.