Datasheet

78K0/Ix2 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0010EJ0500 Rev.5.00 703
Feb 28, 2012
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
28.4.2 Serial interface
(T
A = 40 to +105C, 2.7 V  VDD  5.5 V, AVREF  VDD, VSS = AVSS = 0 V)
(a) UART6/DALI (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 625 kbps
(b) IICA
Standard Mode High-Speed Mode Parameter Symbol Conditions
MIN. MAX. MIN. MAX.
Unit
SCLA0 clock frequency fSCL Fast mode: fPRS  3.5 MHz,
Normal mode: f
PRS  1 MHz
0 100 0 400 kHz
Setup time of start condition and
stop condition
t
SU: STA 4.7

0.6

 s
Hold time
Note 1
tHD: STA 4.0

0.6

 s
Hold time when SCLA0 = “L” tLOW 4.7

1.3

 s
Hold time when SCLA0 = “H” tHIGH 4.0

0.6

 s
Data setup time (reception) tSU: DAT 250

100

ns
Data hold time (transmission)
Notes 2,3
tHD: DAT 0 3.45 0 0.9  s
Setup time of stop condition tSU: STO 4.0

0.6

 s
Bus free time between stop
condition and start condition
t
BUF 4.7

1.3

 s
Rise time of SDAA0 and SCLA0
signals
t
R 1000
20+
0.1C
b
300 ns
Fall time of SDAA0 and SCLA0
signals
t
F 300
20+
0.1C
b
300 ns
Total load capacitance value of
each communication line (SCLA0,
SDAA0)
C
b 400 400 pF
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of t
HD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
3. The data hold time differs depending on the setting of the IICA low-level width setting register (IICWL).