Datasheet

78K0/Ix2 CHAPTER 27 INSTRUCTION SET
R01UH0010EJ0500 Rev.5.00 684
Feb 28, 2012
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
ZACCY
saddr.bit, $addr16 3 8 9 PC  PC + 3 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16 4

11 PC  PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16 3 8

PC  PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16 3

9 PC  PC + 3 + jdisp8 if PSW.bit = 1
BT
[HL].bit, $addr16 3 10 11 PC  PC + 3 + jdisp8 if (HL).bit = 1
saddr.bit, $addr16 4 10 11 PC  PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16 4

11 PC  PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16 3 8

PC  PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16 4

11 PC  PC + 4 + jdisp8 if PSW. bit = 0
BF
[HL].bit, $addr16 3 10 11 PC  PC + 3 + jdisp8 if (HL).bit = 0
saddr.bit, $addr16 4 10 12 PC  PC + 4 + jdisp8 if (saddr.bit) = 1
then reset (saddr.bit)
sfr.bit, $addr16 4

12 PC  PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr16 3 8

PC  PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr16 4

12 PC  PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
  
BTCLR
[HL].bit, $addr16 3 10 12 PC  PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
B, $addr16 2 6

B  B  1, then
PC  PC + 2 + jdisp8 if B  0
C, $addr16 2 6

C  C 1, then
PC  PC + 2 + jdisp8 if C  0
Conditional
branch
DBNZ
saddr, $addr16 3 8 10 (saddr)  (saddr)  1, then
PC  PC + 3 + jdisp8 if (saddr)  0
SEL RBn 2 4

RBS1, 0  n
NOP 1 2

No Operation
EI 2

6 IE  1 (Enable Interrupt)
DI 2

6 IE  0 (Disable Interrupt)
HALT 2 6

Set HALT Mode
CPU
control
STOP 2 6

Set STOP Mode
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
CPU) selected by the processor clock control
register (PCC).
2. This clock cycle applies to the internal ROM program.