Datasheet

78K0/Ix2 CHAPTER 27 INSTRUCTION SET
R01UH0010EJ0500 Rev.5.00 682
Feb 28, 2012
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
ZACCY
CY, saddr.bit 3 6 7 CY  CY  (saddr.bit)

CY, sfr.bit 3

7 CY  CY  sfr.bit

CY, A.bit 2 4

CY  CY  A.bit

CY, PSW.bit 3

7 CY  CY  PSW.bit

AND1
CY, [HL].bit 2 6 7 CY  CY  (HL).bit

CY, saddr.bit 3 6 7 CY  CY  (saddr.bit)

CY, sfr.bit 3

7 CY  CY  sfr.bit

CY, A.bit 2 4

CY  CY  A.bit

CY, PSW.bit 3

7 CY  CY  PSW.bit

OR1
CY, [HL].bit 2 6 7 CY  CY  (HL).bit

CY, saddr.bit 3 6 7 CY  CY  (saddr.bit)

CY, sfr.bit 3

7 CY  CY  sfr.bit

CY, A.bit 2 4

CY  CY  A.bit

CY, PSW. bit 3

7 CY  CY  PSW.bit

XOR1
CY, [HL].bit 2 6 7 CY  CY 
(HL).bit

saddr.bit 2 4 6 (saddr.bit)  1
sfr.bit 3

8 sfr.bit  1
A.bit 2 4

A.bit  1
PSW.bit 2

6 PSW.bit  1
  
SET1
[HL].bit 2 6 8 (HL).bit  1
saddr.bit 2 4 6 (saddr.bit)  0
sfr.bit 3

8 sfr.bit  0
A.bit 2 4

A.bit  0
PSW.bit 2

6 PSW.bit  0
  
CLR1
[HL].bit 2 6 8 (HL).bit  0
SET1 CY 1 2

CY  1 1
CLR1 CY 1 2

CY  0 0
Bit
manipulate
NOT1 CY 1 2

CY  CY

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
CPU) selected by the processor clock control
register (PCC).
2. This clock cycle applies to the internal ROM program.